With asynchronous packet arrivals, we nd that, when the number of packet its is close to the fan-in of the crossbar switch, performance of a non-multiport central bu er switch becomes comparable to its multiport counterpart. Assuming the same amount of bu er memory, simulations of oblivious routing on hypercube indicate that split input bu ering outperforms central bu ering, even when dedicated...

We address the problem of scheduling unsplittable flows using a number of switches in parallel. This has applications in optical switching and eliminates the need for re-sequencing in traditional packet switching. The use of parallel switches is becoming increasingly popular [1], [2] since it provides a way of building a high-speed switch while overcoming the speedup requirement imposed on the ...

ATM switches have been proposed as the switching fabric cores of many high-performance IP switches. In this paper, we present an efficient algorithm called IPPIM for scheduling variable-length IP packets on these switches and compare its performance with the original parallel iterative matching (PIM) ATM cell scheduling algorithm. The mean IP packet delays using both the PIM and the IP-PIM sche...

This Paper focused on Buck/Boost Rectification by Single Phase Matrix Converter with fewer numbers of switches. The conventional matrix converter consists of 4 bidirectional switches, i.e. 8 set of IGBT/MOSFET with anti parallel diodes. In this proposed matrix converter, only six switches are used. The switch commutation arrangements are also carried out in this work. The gate pulses to the swi...

In this paper we present a novel parallel arithmetic architecture using an efficient non-binary logic scheme. We show that by using parallel broadcasting (or domino propagating) state signals, on short reconfigurable buses equipped with a type of switches, called GP (generate-propagate) shift switches, several arithmetic operations can be carried out efficiently. We extend a recently proposed s...

Collective communication performance is critical for many applications. In this paper, we present an architecture to efficiently support collective operations (like multicasts and reductions) in the switches of parallel computer interconnects. We present an output queuing switch architecture with cross-point buffering. Output queuing architectures have been less popular in the past as they requ...