Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technolog...

Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technolog...

In this paper, a single precision IEEE 754 floatingpoint multiplier with high speed and low power is presented. The bottleneck of any single precision floating-point multiplier design is the 24x24 bit integer multiplier. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 24x24 bit multiplication operation is...

A bit parallel systolic multiplier in the finite field GF(2) over the polynomial basis where irreducible polynomial generate the field GF(2) is presented. The complexity of the proposed multiplier is compared in terms of area, latency and speed. The proposed multiplier has high throughput as compared with the traditional systolic multiplier. Moreover, this multiplier is highly regular, modular,...

ÐThe Massey-Omura multiplier of GF …2m† uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another. In the past, it was shown that, for a class of finite fields defined by irreducible all-one polynomials, the parallel Massey-Omura multiplier had redundancy and a modified architecture o...

We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices ofthe phasemode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This ...