Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control ow of existing parallel pattern...

The work reported in this paper is motivated towards validating an alternative approach for fault tolerance over traditional methods like checkpointing that constrain efficacious fault tolerance. Can agent intelligence be used to achieve fault tolerant parallel computing systems? If so, “What agent capabilities are required for fault tolerance?”, “What parallel computational tasks can benefit f...

An efficient method of parallel fault simulation for combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which allow to represent gate level circuits at higher macro level where macros represent subnetworks of gates. Converting the gate-level circuits to the macrolevel is accompanied with corresponding fault collapsing. A parallel fault analysis algo...

FACTS technology has considerable applications in power systems, such as; improving the steady stateperformance, damping the power system oscillations, controlling the power flow, and etc. STATCOM is oneof the most important FACTS devices used in the parallel compensation, enhancing transient stability andetc. Since three phase fault is widespread in power systems, in this paper STATCOM is used...

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults. Keywords-digital c...

Fault simulation is a compute-intensive problem. Data parallel simulation on multiple processors is one method to reduce fault simulation time. In this paper , we discuss a novel technique to partition the fault set for data parallel fault simulation. When applied statically, the technique can scale well for up to eight processors. The fault set partitioning technique is simple, can itself be p...

Described is a method of parallel pattern fault simulation for synchronous sequential circuits that is based on parallel pattern single fault propagation for combinational circuits as described in [1]. This method of fault simulation was proposed in two independent works published in 1991 [2] and 1992 [3] that were a mere three months apart. In this paper this method shall be referred to as PAR...

We propose three synchronous parallel algorithms for scalable parallel test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors. The test set partitioning inherent in the algorithms overcomes the good circuit logic simulation bottl...

EEcient parallel algorithms proposed to solve many fundamental problems in scientiic computation are sensitive to processor failures. Because of its low costs, algorithm-based fault tolerance i s a n i n t e r esting concept for introducing fault tolerance into existing multi-processors. To facilitate fault{tolerant programming in scientiic computation, we have modiied and developed further an ...

This paper presents two novel hybrid schemes for component fault diagnosis in a general nonlinear system. Unlike most fault diagnosis techniques, the proposed solution detects, isolates, and identifies the severity of faults in the system within a single integrated framework. The proposed technique is based on a bank of adaptive neural parameter estimators (NPE) and a set of parameterized fault...