A digitally programmable rail-to-rail CMOS operational amplifier (Op Amp) is designed using standard 0.35 um CMOS process. By using an efficient MOS capacitor is used to compensate the stability of the Op Amp. A compensation current switch is used to adjust the slew rate. Using the schemes, the Op Amp can obtain improved the stability, bandwidth, slew rate and settling time according to the out...

A CMOS voltage controlled Op-Amp oscillator based on N-stage single-ended chain of different inverter types is described in this paper. This paper describes a performance and comparison of a ring oscillator based VCO and an Op-Amp based oscillator based VCO. The VCO is intended to operate in a op-amp based VCO to generate local oscillator frequency for an system. An oscillator topology an impro...

In an era of discrete tube or transistor op-amp modules, any potential advantage to be gained from fully-differential circuitry was masked by primitive op-amp module performance. Fullydifferential output op-amps were abandoned in favor of single ended op-amps. Fully-differential op-amps were all but forgotten, even when IC technology was developed. The main reason appears to be the simplicity o...

The operational amplifier is perhaps the most useful integrated device in existence today. It is widely used in analogue computers, simulation systems and in a variety of electronic applications such as filtering, buffering and comparison of signal levels. In this paper, the different schemes of power-efficient class AB two-stage op-amps using a current replication branch and adaptive loads wer...

In this paper the challenge of enhancing the gain and reducing the power requirement of amplifiers, preferably used in biomedical applications is addressed by demonstrating that composite cascode stages, operating in subthreshold/weak inversion regions provide a method of designing a ultra high gain (97dB) and low-power (21μW) op amp with 1.5V power supply. The op amp is designed without compen...

In this paper, CMOS Sample-and-Hold (S/H) is presented. The S/H circuit is an important component in Analog-to-digital Converter (ADC). In low frequency application, the boost clock technique is used to constitute a rail-to-rail signal voltage with low distortion. The operational amplifier works as a unity gain buffer in the S/H circuit. However, a two-stage op-amp is proposed with enhanced low...

This paper describes a single op-amp 0+2 ⌃ architecture and design considerations to achieve 12-b resolution on a 2-MHz bandwidth. The proposed topology combines op-amp reduction and MASH techniques. In particular, the second-order ⌃ stage uses direct synthesis of the noise transfer function (NTF) and employs only one op-amp. The use of multi-bit quantization on both stages increases the resolu...

This paper presents a novel methodology of simulation and realization of a various Op-amp topologies, such as two-stage, telescopic and folded cascade are discussed in this paper. The aim of the present work is the development of a tool box which contains the Matlab code to allow automated synthesis of Analog circuits. This tool box is used to find the transistor dimensions (i.e.., width and le...

The sigma delta technique is an attractive approach for many communication applications. The possible alternatives are the use of continuous-time or sampled data modulators. This paper discusses various circuit techniques that enable very low power with switched capacitor architectures. The target applications are WCDMA and ADSL. Circuit implementations show that the use of techniques like use ...

A frequency compensation technique for the improvement of unity gain bandwidth (UGB) and power supply rejection ratio (PSRR) of two stage operational amplifiers is presented in this paper. Performance of proposed op-amp is compared with classical miller compensated op-amp and op-amp proposed by G. Blakiewicz [13]. The technique exploits the triode mode operation of a MOSFET in the compensation ...