Data Envelopment Analysis (DEA) is a nonparametric approach for measuring the relative efficiency of a decision making units consists of multiple inputs and outputs. In all standard DEA models semi positive real valued measures are assumed, while in some real cases inputs and outputs may take complex valued. The question is related to measuring efficiency in such cases. As far as we are aware, ...

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative ...

We propose an algorithm for ihe design of multiplevalued current-mode CMOS logic (CMCL) circuiis that i s based on the cost-fable iechnique. The a1 orithm is a heuristic search technique AO' algorithm) L O , l l ] apExhaustive Search while providing realizations that are almost as good. A new cost-table is also proposed ihai results in better realizations ihan obtained with a previous cost-tabl...

In this paper the Event-oriented Logic, an innovative approach to system design, is presented. It is proposed for the first time to give to both signal levels and signal transitions a logical meaning, so that the information content per wire is increased as in multiple-valued logic. The new technique is applied to asynchronous systems and possible handshake models have been studied. One of thes...

A novel methodology designing for Multiple-Valued Logic voltage-mode storage circuits is introduced. Using the proposed inverter-based unit, uni-signal controlled pass gates and True Single-Phase Clocked Logic-based output units, efficient r-ary (where r is the radix) dynamic and pseudo-static latches can be designed. They exhibit regular, modular, and iterative structure, which means that the ...

The proposed two types of multi-valued D flip-flops are NMAX-TG D flip-flop and NMIN-TG D flip-flop A NMAX-TG D flip-flop and a NMIN D flip-flop are composed of the components such as NMAX D flip-flops, NMIN D flip-flops and T-gate circuits. In the simulations, sampling frequencies of NMAX-TG D flip-flop and NMIN-TG D flip-flop are measured around 500 kHz and 1 MHz, respectively. The PDP parame...

This paper describes the design and analysis of three types of multiple-valued PLA’s: ‘lype 1 PLA’s realize functions directly in the form of the MAX of MIN of literal functions and constants. In Type 2 PLA’s, the body of the PLA is binary and the output is encoded as a multiple-valued logic value. ‘fype 3 PLA’s are the same as 5pe 2 PLA’s except 2-bit decoders and a permutation network is used...

In this paper we review the development & advantages of multi valued logic. The multi valued logic has been object of research over last few decades. Since 1971 there have been annual symposiums on multi valued logic. The use of non binary logic or discrete-analog signal processing is not out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. ...