We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intend...

Advanced CMOS processes offer very fast switching speed and high transistor density that can be utilized to implement analog signal processing functions in interesting and unconventional ways, for example by leveraging time as a signal domain. In this context, voltage controlled ring oscillators are circuit elements that are not only very attractive due to their highly digital implementation wh...

This study examines how multisensory stimuli affect the performance of children with Developmental Coordination Disorder (DCD) on a choice reaction time (CRT) task. Ten children with DCD, identified using the Movement Assessment Battery for Children-2, aged 7-10 years (4F, M=8 y 3 m, SD=17 m) and 10 typically developing peers (TDC) (5F, M=8 y 4 m, SD=17 m) reached to unimodal (auditory (AO), vi...

A new learning scheme called time divergence-convergence – TDC – is proposed for two-layer dynamic synapse neural networks – DSNN. DSNN is an artificial neural network model, in which the synaptic transmission is modeled by a dynamic process and the information between neurons are transmitted through spike timing. In TDC, the intra-layer neurons of a DSNN are trained to map input spike trains t...

Abstract This paper proposes a hybrid robust-adaptive learning-based control scheme based on Approximate Dynamic Programming (ADP) for the tracking of autonomous ship maneuvering. We adopt Time-Delay Control (TDC) approach, which is known as simple, practical, model free and roughly robust strategy, combined with an Actor-Critic (ACADP) algorithm adaptive part in proposed algorithm. Based this ...

A novel multi-stage noise-shaping (MASH) delta-sigma (∆Σ) Time-to-Digital Converter (TDC) structure is proposed for applications in continuous-time pulsed time-offlight (TOF) rangefinders for nuclear reactor remote sensing, which requires both high resolution and multi MGy gamma-dose radiation tolerance. The converter, implemented in 0.13 μm CMOS, achieves a time resolution of 5.6 ps and an ENO...

In the scope of the COMPASS experiment a multi-purpose, high rate capable TDC with digitisation width of 60 ps has been developed. The integration into the readout system and the flexible input of the CATCH readout driver is presented.

This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work. The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the ...

We propose using multi-scale image textures to investigate links between neuroanatomical regions and clinical variables in MRI. Texture features are derived at multiple scales of resolution based on the Laplacian-of-Gaussian (LoG) filter. Three quantifier functions (Average, Standard Deviation and Entropy) are used to summarize texture statistics within standard, automatically segmented neuroan...

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps 800ps bin) has been implemented in a 0.25um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 98ps. Finally, finer time interpolation is obtained using an on-c...