Several recent device technology developments have been fundamentally changing the microprocessor architecture design space. These developments include photonic interconnects, feature size reduction, 3D fabrication, and aggressive energy management. These technologies create a large parameter space of possible future architectures. The focus of this talk and research effort is to demonstrate a ...

Efficient parallelization of genetic algorithms (GAs) on state-of-the-art multi-threading or many-threading platforms is a challenge due to the difficulty of schedulation of hardware resources regarding the concurrency of threads. In this paper, for resolving the problem, a novel method is proposed, which parallelizes the GA by designing three concurrent kernels, each of which running some depe...

In this article, we present a novel distributed memory tridiagonal solver library, targeting large-scale systems based on modern multicore and many-core processor architectures. The library uses methods both approximate exact algorithms. Performance comparisons with the state of art, using large Cray EX system GPU cluster show algorithmic tradeoffs required at increasing machine scale to achiev...

Word2vec is a widely used algorithm for extracting low-dimensional vector representations of words. State-of-the-art algorithms including those by Mikolov et al. [5, 6] have been parallelized for multi-core CPU architectures, but are based on vector-vector operations with “Hogwild" updates that are memory-bandwidth intensive and do not efficiently use computational resources. In this paper, we ...

Power managing is a major issue in designing the future asymmectric multi/many-core processors. The challenge is to provide a solution that has low power consumption, in addition to trade off a small decrease in performance and throughput. Our design includes asymmetric cores in consideration of different points in the view of power-performance efficiency during an application’s execution. In t...