This paper proposes a new test data compression method for low power testing. To improve compression ratio, the proposed scheme uses the modified input reduction and novel techniques, a new scan flip-flop reordering algorithm and a newly proposed one block compression. The proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous wo...

Power consumption has become the most important issue in the design of integrated circuits. The power consumption during manufacturing or in-system test of a circuit can significantly exceed the power consumption during functional operation. The excessive power can lead to false test fails or can result in the permanent degradation or destruction of the device under test. Both effects can signi...

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...

scaling challenges and limitations of conventional silicon transistors have led the designers to apply novel nano-technologies. one of the most promising and possible nano-technologies is cnt (carbon nanotube) based transistors. cnfet have emerged as the more practicable and promising alternative device compared to the other nanotechnologies.  this technology has higher efficiency compared to t...