We demonstrate field-effect transistors using heterogeneously stacked two-dimensional materials for all of the components, including the semiconductor, insulator, and metal layers. Specifically, MoS2 is used as the active channel material, hexagonal-BN as the top-gate dielectric, and graphene as the source/drain and the top-gate contacts. This transistor exhibits n-type behavior with an ON/OFF ...

Floating-Gate Memory In article number 2105472, Young-Jun Yu and co-workers systematically design demonstrate multiple bits on non-volatile memory based vdW heterostructure floating-gate (FGM) by tuning the dimensions of 2D materials. A fingerprint mechanism is established that links bit crystals heterostructures. This approach could enable precise generation desired in layered-material-based F...

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data–reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction of logic and interconnects requiremen...

2D layered GaTe materials have attracted a great deal of attention for optoelectronic applications due to their direct band structure, whether in bulk or as a single layer. In this paper, for the first time, we have synthesized high quality, single crystalline GaTe nanosheets by employing a facile CVD method. The size of the GaTe nanosheets reached several tens of micrometers, and some of them ...

A quantum model based on solutions t o t he SchrÊdinger2Poisson equations is develop ed t o investigate t he device behavior related t o gate tunneling cur rent f or nanoscale MOS F ETs wit h high2 k gate stacks . This model can model various MOS device st ructures wit h combinations of high2 k dielect ric materials and multilayer gate stacks , revealing quantum effects on t he device perf orma...

One of the major yield killers of power-amplifier PHEMTbased MMICs is fabricating a T-shaped gate with gate periphery of several tens of mm. We have investigated a novel PMMA/PMGI/PMMA tri-layer resist scheme for T-Gate definition of PHEMTs with 0.25-μm gate length and in-situ Ar ion beam treatment before gate evaporation as methods for eliminating this problem. We intend to extend this technol...

Improvement of the electrical and photoelectric characteristics is essential to achieve an advanced performance of field-effect transistors and optoelectronic devices. Here we have developed a doping technique to drastically improve electrical and photoelectric characteristics of single-layered, bi-layered and multi-layered WS2 field-effect transistors (FET). After illuminating with deep ultrav...

Two-dimensional layered materials including graphene and transition metal dichalcogenides are identified as promising candidates for various electronic and optoelectronic applications. Due to the weak coupling between individual layers, large contact resistances are frequently found and dominate the performance of layered material systems. In this paper, we employ few-layer graphene as an examp...