A characterization of a state of the art pipeline ADC is presented. Measurements are performed on a wide set of frequencies. The integral non linearity (INL) is modeled by high code and low code components, HCF and LCF. The HCF component is to be deprived of any dynamic behavior, and varies piecewise linearly in certain intervals. Hence, the LCF represents the dynamic behavior that should varie...

− This paper investigates the statistical properties of quantization noise. In particular, a theoretical model is discussed, which evaluates the power of quantization noise introduced by a memoryless Analog to Digital Converter (ADC) as a function of both the converted signal distribution and the ADC thresholds positioning. Expressions have also been derived to express the Integral Non-Linearit...

Measurement of integral non-linearity (INL) and differential non-linearity (DNL) of an A/D converter using the histogram method incurs large test time. This test time can be a significant percentage of the total test time, especially for high resolution and low sampling-speed A/D converters. This paper describes a test methodology for measuring the INL and DNL specifications of A/D converters b...

The Analog to digital converter (ADC) has been widely used in all kinds of modern electronic instruments and it is desirable to study the relationship between different errors and performance of an ADC. This paper studies the relationships between integral non-linearity (INL) error and signal to noise ratio (SNR), and the relationship between non-linearity (DNL) error and SNR after Midpoint met...

This paper proposes a random shifting data weighted averaging (RSDWA) algorithm where bidirectional circular shift register is co-worked with pseudo-random sequencer to form module, which makes mismatch error suppressed in the frequency domain, therefore it can achieve higher Spurious Free Dynamic Range (SFDR) compared traditional DWA. To verify proposed algorithm, 6-bit Nyquist-rate resistor l...

This paper presents an 8-b 20-Msample/s pipelined analog-to-digital converter (ADC) designed in 0.5-μm CMOS technology. On first silicon this converter achieved 7.8 effective-number-of-bits (ENOB), a peak differential-non-linearity (DNL) of -0.36LSB and integralnon-linearity (INL) of 0.35LSB.

Abstract A high-resolution clock phase shifter is implemented to adjust the of multiple clocks at 40 MHz, 80 or 640 MHz in ALTIROC chip. The has a coarse-phase and fine-phase achieve step size 97.7 ps an adjustable range 25 ns. fine delay unit based on Delay Locked Loop (DLL) operating MHz. fabricated 130 nm CMOS process. area 725 µm × 248 µm. Differential Non-Linearity (DNL) Integral (INL) are...

The accuracy of a Digital to Analog Converter (DAC) is crucial for its operation. Due to production tolerances [1], the DAC static accuracy is limited, increasing the Integral Non-Linearity (INL). Traditionally, various calibration techniques are used to improve the INL [2]. In a Current Steering (CS) DAC, the output signal is generated by switchable current sources, the current cells, see Fig....

In this paper an analytic approach to estimate the nonlinearity of radix-4 pipelined analog-to-digital converters due to the circuit non-idealities is presented. Output voltage of each stage is modeled as sum of the ideal output voltage and non-ideal output voltage (error voltage), in which non-ideal output voltage is created by capacitor mismatch, comparator offset, input offset, and finite ga...

* This work was supported, in part, by Texas Instruments Inc., Rocketchips Inc, and the R. J. Carver trust. Abstract A new algorithm based on a code density test to measure Integral Non-linearity (INL) of Analog-to-Digital (A/D) converters is introduced. This algorithm uses as an input two related but unknown ‘ramp-like’ signals that can be practically generated on-chip and the corresponding co...