Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are illsuited to pipelined or parallel instruction fetch and decode. However, heads-and-tails (HAT) is a new variable-length instruction format that supports parallel fetch and decode of multiple instructions per cycle, allowing both high code density and rapid execution for high-performanc...

The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past decade. Instead, larger unified L2 and L3 caches were introduced. This cache hierarchy has a high overhead due to the principle of containment, as all the cache blocks in the upper level caches are contained in the lower...

Designing a Java processor supporting horizontal multithreading has been becoming more attractive as network computing gains importance. Different from the traditional superscalar processors that issue multiple instructions from a single instruction stream to exploit the instruction level parallelism (ILP), the horizontal multithreading Java processors issue multiple instructions (bytecodes) fr...

The objective of this paper is to improve the use of the hardware resources of the trace cache mechanism, reducing the implementation cost with no performance degradation. We achieve that by eliminating the replication of traces between the instruction cache and the trace cache. As we show, the trace cache mechanism is generating a high degree of redundancy between the traces stored in the trac...

Instruction cache performance is important to instruction fetch efficiency and overall processor performance. The layout of an executable has a substantial effect on the cache miss rate and the instruction working set size during execution. This means that the performance of an executable can be improved significantly by applying a code-placement algorithm that minimizes instruction cache confl...

Contemporary computing architectures make an extensive use of cache memories to cope with the increasing speed gap between the processing power of the processing element and the bandwidth of the memory subsystem. In a fixed-priority preemptive real-time system, in addition to obtaining logically correct results, it is also mandatory to satisfy timing constraints. Since the contents of the cache...

Our project starts from investigating if instruction-based sharing exists on commercial workloads such as Apache, Zeus, Jbb, and Oltp running on CMPs. We find that there is a large amount of instruction-based sharing on CMPs. Constructive interference at the instruction cache miss level also exists among different CMP cores. We further study if the implementation of a shared Markov table can he...

Instruction fetch mechanism is a performance bottleneck of a Superscalar Processor. Fetch performance can be improved with the aid of an instruction memory known as a Trace Cache. This paper presents analytical expressions, which describe instruction fetch performance of a Trace Cache microarchitecture. The instruction fetch rates predicted by the expressions differ by seven percent from the si...