For the 45nm technology node, high-k+metal gate transistors have been introduced for the first time in a high-volume manufacturing process [1]. The introduction of a high-k gate dielectric enabled a 0.7x reduction in Tox while reducing gate leakage 1000x for the PMOS and 25x for the NMOS transistors. Dual-band edge workfunction metal gates were introduced, eliminating polysilicon gate depletion...

Abstract In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between the body and drain. Lateral S/D...

Intrinsic parameter fluctuations on device characteristic and yield are crucial in determining the operation of nanoscale semiconductor devices. In this paper, we examine the fluctuations of the threshold voltage (Vth), gate capacitance (Cg), and cutoff frequency (FT) of emerging metal/high-κ gate planar complementary metal-oxidesemiconductor (CMOS) field effect transistors (FETs) variability i...

In this paper, we explore the quantitative investigation of the high-frequency performance of Gate Electrode Workfunction Engineered (GEWE) Silicon Nanowire (SiNW) MOSFET and compared with Silicon Nanowire MOSFET(SiNW MOSFET) using device simulators: ATLAS and DEVEDIT 3D. Simulation results demonstrate the improved RF performance exhibited by GEWE-SiNW MOSFET over SiNW MOSFET in terms of transc...

To meet the gate leakage specifications in the International Technology Roadmap for Semiconductors (ITRS), an intensive search is being conducted for alternative gate stack materials. Most of the studies have focused on basic material properties, but very little effort has been directed towards quantifying and understanding the effect of post metallization annealing (PMA) on the electrical prop...

High-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively explores the physics and mechanism of the intrinsic parameter fluctuations in nanoscale fin-type field-effect transistors by using an experimentally validated three-dimensional quantum-corrected device simulation. The dominance fluctuation sources in threshold vo...

Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the last decade offering superior CMOS devices with higher speed, higher density, excellent radiation hardness and reduced second order effects for submicron VLSI applications. Recent experimental studies have invigorated interest in fully depleted (FD) SOI devices because of their potentially superior scalability rela...

Abstract: In this paper, a novel tunnel field effect transistor (TFET) is introduced, thatdue to its superior gate controllability, can be considered as a promising candidate forthe conventional TFET. The proposed electrically doped heterojunction TFET(EDHJTFET) has a 3D core-shell nanotube structure with external and internal gatessurrounding the channel that employs el...

In this paper, the electrical characteristics and sensitivity analysis of staggered type p-channel heterojunction electron-hole bilayer tunnel field effect transistor (HJ-EHBTFET) are thoroughly investigated via simulation study. The minimum lattice mismatch between InAs/GaAs0.1Sb0.9 layers besides low carrier effective mass of materials provides high probability ...

It has been clear for a number of years that increasing transistor gate leakage with device scaling would ultimately necessitate an alternative to traditional SiON dielectrics with polysilicon gates. Material systems providing higher dielectric constants, and therefore allowing physically thicker dielectrics, have been the object of extensive research. Such high-k dielectrics, when combined wit...