In this paper, we describe a novel circuit consisting of N + 1 MOS transistors and a single floating gate which computes n soft maximumof N current inputs and reflects the result in the output transistor. An intuitive description of the operation of the circuit is given. Data from a working two-input version of the circuit is presented and discussed. The circuit features a high output voltage s...

As the size of a transistor continuously scales down, single electron effects become important [1 – 3]. Previously, we have studied charge transport in single-electron quantum dot transistors which have a channel consisting of a silicon dot separated from the source and the drain by two constrictions [4], and in single-electron MOS memories that have a polysilicon dot floating gate stacked on a...

In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a draidsource current decomposition. A fronthack-gate current decomposition is adopted; this facilitates the analysis of translinea...

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-...

The implementation of large-valued floating resistive elements using MOS transistors in subthreshold region is addressed. The application of these elements to bias wideband AC coupled amplifiers is discussed. Simple schemes to generate the gate control voltages for the MOS transistors implementing large resistors so that they remain in high resistive state with large signal variations are discu...

In this paper a new synthesis for circuit design of Euclidean distance calculation is presented. The circuit is implemented based on a simple two-quadrant squarer/divider block. The circuit that employs floating gate MOS (FG-MOS) transistors operating in weak inversion region, features low circuit complexity, low power (<20uW), low supply voltage (0.5V), two quadrant input current, wide dyn...

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. Th...

Nanometer-size Si quantum dots (Si-QDs) with and without Ge core were prepared on thermally-grown SiO2 in a self-assembling manner by controlling the early stages of low pressure chemical vapor deposition (LPCVD). The surface potential changes in individual dots caused by charging or discharging of one electron or a few as were measured by using a Kelvin probe technique in an atomic force micro...

This paper presents the design of a low power second-order continuous-time sigma-delta modulator for low power applications. The loop filter of this modulator has been implemented based on the nonlinear transconductance-capacitor (Gm-C) by employing current-mode technique. The nonlinear transconductance uses floating gate MOS (FG-MOS) transistors that operate in weak inversion region. The propo...