The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other exis...

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1μ technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing ...

Most digital systems textbooks treat the topic of converting one flip flop to another by simply giving the student certain simple conversion circuits, such as the use of an inverter between the R and S inputs of an RS flip flop to form a D flip flop, or tying together the inputs of a JK flip flop to make a T flip flop. However, a more general, but very simple, methodology for flip flop conversi...

A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson [I], in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The ad...

In digital VLSI system the clock distribution network and flip flops are most power consuming components. The reduction of power consumption by clock distribution networks & flip flop makes the total VLSI system as low power VLSI system. In the earlier VLSI system design, different power consumption methods are followed to design the various flip-flops .The SABFF(sense amplifier based flip flop...

The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of this project is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC’s of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is ...

Power dissipation of IC during test mode is greater than the IC’s normal mode of functioning. Power consumption in scan based testing is high due to the toggling of the combinational logic during the scan shift.In digital systems power reduction is the most critical issue. A FLIP FLOP is a one bit storage device used for storage device used for storage purpose. Mostly used d-flip flop in digita...

In this paper, we examine the problems in the CDN of the flip flop & design an improved CDN oriented Flip-flop which is Clocked Pair Shared Flip Flop (CPSFF). Clock Division Network (CDN)’S plays an important role in the flip flop design and it’s the major element in the flip –flop for producing the logical outputs it’s much important to design the CDN with low power and area. Power consumption...

Power reduction has become a vital design goal for sophisticated design applications, whether mobile or not. dropping power consumption in design enables better, cheaper products to be designed and power-related chip failures to be minimized. Researchers have shown that multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-fl...