We present a scalable, dynamically reconfigurable processor design that encompasses both reconfigurable circuitry and software-capable programmability for supercomputing applications on FPGAs. Advanced FPGA chips contain both reconfigurable logic blocks and embedded processor cores, providing the developer with an environment for embedded system design1. Since the reconfigurable fabric and the ...

A major challenge in realizing core-based system-chips is the adoption of adequate test and diagnosis strategies. this paper focuses on the current industrial practices in test strategies for system-chips. It discusses the challenges in testing embedded cores, the testing requirements for individual cores, and their test access mechanisms. It also covers the integrated test strategies for syste...

For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementa...

Based on the theories of social representation (SC) and Central Core (CC), a structural study was undertaken regarding the neologism hanseniase (Hansen's disease), the term adopted by Brazil's Ministry of Health in the 1970s. Carried out during 2001, this study interviewed eight hundred housewives residing in the Rio de Janeiro and Duque de Caxias municipalities. It found that Hansen's disease ...

This investigation discusses the findings on analysis results of a pavement structure constructed on a relatively expansive material consisting mainly of brown clayey silt in Tebessa, Algeria. Cores were brought to the laboratory from a piece of roadwork. Remolded samples were taken from subgrade of a deteriorated road. The soils were generally found to be of medium plasticity and of a medium t...

1 We integrate scan-chain partitioning and preemptive test access mechanism (TAM) scheduling for core-based systems under power constraint. We also outline a flexible power conscious test wrapper to increase the flexibility in the scheduling process by (1) allowing several different bandwidths at cores and (2) controlling the cores test power consumption, which makes it possible to increase the...

Wepropose a geometric interpretation to the ranking of patent assignees by their h-indices as indicating the relative positions of their rank-citation curves.We thenpropose two shape descriptors characterizing the rank-citation curves over the h-cores and h-tails, respectively. Together with the h-indices, the shape descriptors help verifying the geometric relationship among rank-citation curve...

For flexible mapping of various task-level pipelines on a multi-core processor, the authors proposed the memory-centric network-on-chip (NoC). The memory-centric NoC manages producer–consumer data transactions between the tasks in the case of task-level pipelines are distributed over multiple processing cores. Since the memory-centric NoC manages the data transactions, it relieves burden of the...

in this paper, the behavior of free vibrations and buckling of the sandwich panel with a flexible core was investigated using a new improved ‎high-order sandwich panel theory. in this theory, equations of motion were formulated based on shear stresses in the core. first-order shear deformation theory was ‎applied for the procedures. in this theory, for the first time, incompatibility problem of...

A systematic approach is presented for automatically generating variable-size FFT/IFFT soft intellectual property (IP) cores for MIMO-OFDM systems. The finite-precision effect in an FFT processor is first analyzed, and then an effective word-length searching algorithm is proposed and incorporated in the proposed IP generator. From the comparison, we show that our analysis of the finite precisio...