This paper describes a technique which uses the Differential Non Linearity (DNL) test data for fault location and identification of the analog components of a flash ADC. In a flash ADC, a fault in the analog subcircuit is uniquely reflected in the transfer function and therefore also in DNL data.This property is exploited to locate a fault and to identify the error value in analog components of...

Flash ADC is an important component for realization of high speed and low power devices in signal processing system .As technology scale down, leakage current becomes the most concerned factor. This paper reports the power gating technique to provide the reduction mechanism for suppressing the leakage current effectively during standby mode but it introduces ground bounce noise. We designed a “...

Digital wireless communication applications such as UWB and WPAN necessitate low-power high-speed ADCs to convert RF/IF signals into digital form for subsequent baseband processing. Considering latency and conversion speed, flash ADCs are often the most preferred option. Generally, flash ADCs suffer from high power consumption and large area overhead. On the contrary, SAR ADCs have low power di...

Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonst rated. The first design is a voltage scalable z...

In this paper, Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive divider network and array of differential comparators in conventional flash Analog to Digital Converter (ADC) by an internal comparator constructed Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold serving as voltage...

In modern VLSI design the transistor sizing and scaling has an considerable impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital converter (ADC) in 45nm CMOS technology is presented for low power and high speed system-on-chip (SoC) appli...

In present scenario high speed and low power devices in signal processing system is generally needed the efficient design and reduced complexity of converters, therefore conventional flash ADC is not fully meet the required specifications. ADC with high speed and low resolution is required in present communication technologies. Lower leakage current with low power consumption is considerable ef...

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. T...

Multigigahertz flash ADC is limited by sampling clock timing jitter. Since it is used in high frequency applications it is essential to remove jitter effects which will reduce the efficiency of ADC. This paper describes the effect of clock transition time on the spurious free dynamic range of a CMOS sample and hold circuit. To improve SFDR the effect of finite clock transition time of the signa...