In this paper, a configurable single chip firing circuit for three phase motor speed control based on Field Programmable Gate Array (FPGA) hardware architecture is presented. The proposed circuit is designed, implemented and tested using MAX II PLD chip (EPM1270F256C5 device). The system has the advantages of being simple, flexible and low development cost with built-in self test. The experimen...

Abstract This paper presents a new stochastic model for two dimensional layouts of large size. Two problems are addressed: (i) Under the condition that the number of wires emanating from a block is Poisson distributed, determine the distribution of channel width, thus estimating the average channel width. (ii) Given T tracks for each channel, determine the success probability of routing an M×M ...

A new Field Programmable Gate Array (FPGA) architecture is described. This architecture includes a number of novel features not found in currently available FPGAs. It is believed to ooer a signii-cantly improved logic density in some common applications. This paper describes the development of the FPGA and looks at the mapping onto it of some interesting application circuit elements. The design...

The intention of this paper is to give a short description of the dynamically reconfiguring procedure for a Field Programmable Analogue Array (FPAA) AN221E04 by means of a tested example. [1]

The necessity for programmable analog devices appears when it is necessary to ease the design process in small time and with minimum costs, making the research in FPAAs (Field Programmable Analog Array) more intense. In this work we proposed a new FPAA topology aiming at wide frequency range, while keeping a high degree of reconfigurability. The impact in frequency, programmability and resoluti...

4.