Reversible logic circuits have emerged as a promising technology having its applications in low power CMOS, Quantum Computing, nanotechnology, and optical computing. Power is the major constraint for any circuit Each circuit demands not only low power, but fast speed. This paper is focused on the efficient design of the full Adder/Subtractor with the help of half adder subtractor with single co...

In data processing processors, adder is a basic digital circuit. To perform any arithmetic operation, addition is the basic operation to perform. To compute fast arithmetic operations adder must be fastest. CSLA is the fastest adder when compare to RCA and CLA. From the structure of CSLA it is observed that there is a scope to reduce area further so that power can be lowered [3-4]. This paper p...

Carry free arithmetic using higher radix number system such as Redundant Binary Signed Digit can be used to meet the demand for computers operating at much higher speeds. The computation speed can also be increased by using the suitable design of adder and multiplier circuits. Fast RBSD adder cells suggested by Neelam Sharma in 2006 using universal logic are modified in the proposed design by r...

one the challenging in hardware performance is to designing a high speed calculating unit. the higher of calculations speeds in a computer system  will be pointed out in terms of performance. as a result, designing a high speed calculating unit is of utmost importance. in this paper, we start design whit this knowledge that one multiplier made of several adder and one divider made of several su...

Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corresponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the XOR-sum of the propagate signals. Fo...

Binary adders are the basic and vital element in the circuit designs. Prefix adders are the most efficient binary adders for ASIC implementation. But these advantages are not suitable for FPGA implementation because of CLBs and routing constraints on FPGA. This paper presents different types of parallel prefix adders and compares them with the Simple Adder. The adders are designed using Verilog...

One the challenging in hardware performance is to designing a high speed calculating unit. The higher of calculations speeds in a computer system  will be pointed out in terms of performance. As a result, designing a high speed calculating unit is of utmost importance. In this paper, we start design whit this knowledge that one multiplier made of several adder and one divider made of several su...