The integrity and issues related performance associated with scaling Si MOSFET channel length promotes research in new device SOI, double gate and GAA MOSFET. In this paper, we pr novel characteristic of horizontal rectangular gate MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some para...

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, thicknesses top bottom gate oxide films is derived for asymmetric junctionless double (JLDG) MOSFETs. characteristics between the current voltage by using potential distribution model to propose in this paper. In case, threshold defined as corresponding when (W/L) × 10-7 A, DIBL represent...

This paper explains the performance analysis of Gate-AllAround silicon nanowire with 80nm diameter field effect transistor based CMOS based device utilizing the 45-nm technology. Simulation and analysis of nanowire (NW) CMOS inverter show that there is the reduction of 70% in leakage power and delay minimization of 25% as compared with 180 nm channel length.Gate-All-Aorund (GAA) configuration p...

We report an SRAM with a 90% reduction of activeleakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells,...

The recent development of MOSFET demands innovative approach to maintain the scaling into nanoscale dimension. This paper focuses on the physical nature of vertical MOSFET in nanoscale regime. Vertical structure is one of the promising devices in further scaling, with relaxed-lithography feature in the manufacture. The comparison of vertical and lateral MOSFET performance for nanoscale channel ...

Compact models of short channel effect in symmetric and asymmetric double gate MOSFETs are developed by solving two-dimensional (2-D) Poisson’s equation as a boundary value problem in the subthreshold region. The subthreshold current is obtained through the 2-D analytic potential distribution function. Threshold voltage rolloff, drain induced barrier lowering (DIBL) and subthreshold slope degra...

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar...

<span>This paper studies the impact of fin width channel on temperature and electrical characteristics field-effect transistor (FinFET). The simulation tool multi-gate field effect (MuGFET) has been used to examine FinFET characteristics. Transfer with various temperatures (W<sub>F</sub>=5, 10, 20, 40, 80 nm) are at first simulated in this study. results show that increasing e...

In this work, we study the impact of random interface traps (RITs) at the interface of SiO x /Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of ...

A two-dimensional analytical model for the potential distribution along the bottom channel of the fully depleted region of dual material gate (DMG) SOI MESFET is presented. The potential distribution is modeled by solving the Poisson equation with proper boundary conditions. The model for the potential distribution is extended to derive an analytical expression for the threshold voltage. The ac...