A digital delay-locked-loop (DLL) suitable for generation of multiphase clocks in applications such as timeinterleaved and pipelined ADCs locks in a very wide (40X) frequency range. The DLL provides 12 uniformly delayed phases that are free of false harmonic locking. The digital control loop has two stages: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine...

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-l...

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect...

Analog Delay Line, " has been reviewed in final form. Permission, as indicated by the signatures and dates given below, is now granted to submit final copies to the College of Graduate Studies for approval. ABSTRACT High-speed synchronous interface circuits require that the controlling clock signals be accurately aligned. A dynamic de-skew circuit can be used to ensure good clock alignment acro...

A 3–8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitter...

In this paper, a Delay-Locked Loop (DLL) based clock generator is designed which can be used mainly for dynamic frequency scaling. This DLL-based clock generator is found to have low-jitter and can provide the system clock with frequencies in the range of 0.5 to 8 times of reference clock, depending on the workload of the EISC processor. This proposed analog self-calibration method and a phase ...

In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitt...

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 μ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold times of I/O registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also em...

This paper describes a 1.6GHz clock synthesizer which employs a delay locked loop (DLL) to generate multiple phases that are combined to produce the desired output clock frequency. A self correcting circuit ensures that the DLL arrives at the correct locked state irrespective of its power-up state or following either a wide variation in the input reference clock frequency or missing pulses in t...

Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several d...