This paper proposes “path mapping”, a method of delay estimation for technology independent combinational circuits. Path mapping provides fast and accurate delay estimation using the common ideas with the tree covering based technology mapping. First, path mapping does technology mapping for all paths in the circuit with minimum delay. Then, it finds the most critical path among all the paths i...

Accurate delay calculation of circuit gates is very important in timing analysis of digital circuits. Waveform shapes on the input ports of logic gates should be considered, in the characterization phase of delay calculation, to obtain accurate gate delay values. Glitches and their temporal effect on circuit gate delays should be taken into account for this purpose. However, the explosive numbe...

In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in...

A time-delay chaotification approach can be applied to the Chua’s circuit by adding a small-amplitude time-delay feedback voltage to the circuit. The chaotic dynamics of this newly derived time-delay Chua’s circuit is studied by theoretical analysis, verified by computer simulations as well as by circuit experiments.

this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit f...

residue number system (rns) is a carry-free and non-weighed integer system. in this paper an improved three-moduli set  in reverse converter based on crt algorithm is proposed. crt algorithm can perform a better delay and hardware implementation in modules via other algorithms. this moduli is based on p that covers a wide range on modules and supports the whole range of its modules in dynamic r...

A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. A feature of semi-synchronous circuits is that the minimum delay between registers may be critical with respect to the clock period of the circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum...

5.1 Introduction The increasing circuit operating frequencies and demands for low cost and high quality require that the temporal correctness of the circuit can be guaranteed. For high performance circuits with aggressive timing requirements, small process variations can lead to failures at the design clock rate. These defects can stay un-detected after at-speed or stuck-at-fault testing. Delay...

Circuit delay computation taking into account the existence of false paths represents a significant and computationally complex problem. Existing research work has focused mainly on path sensitization models and algorithms, and on gate and interconnect delay models. Nevertheless, work in these two main areas has evolved separately, and so most path sensitization models and algorithms assume ver...

Abstract This paper is concerned with a linear time-delay circuit and its feedback control. We use electronic components such as resistors capacitors to realize system. The time-delays are generated by operational amplifiers single-chip microcomputers. Based on the actual data measured oscilloscope, parameters of system estimated using least square method. Then comparison study between waveform...