In deep submicron VLSI designs, cross capacitance between adjacent wires becomes the dominant factor in determining chip performance and power consumption. Consequently, traditional floorplanning algorithms, which typically optimize for die area and ignore wire congestion, become inadequate in deep submicron era. Based on a stochastic congestion model, we propose a floorplanning algorithm that ...

The purpose of the present investigation was to study the aerosolization, lungs deposition and pharmacokinetic study of inhalable submicron particles of budesonide in male Wistar rats. Submicron particles were prepared by antisolvent nanoprecipitation method and freeze-dried to obtain free flowing powder. The freeze-drying process yielded dry powder with desirable aerodynamic properties for inh...

Understanding ferroelectricity at the deep submicron regime is desirable in utilizing it for next generation nonvolatile memory devices, medical imaging systems, and rf filters. Here we show how piezoresponse force microscopy can be enhanced 1 nm resolution . Using this method, we have investigated ferroelectric and ferroelastic domains at the deep submicron regime in polycrystalline lead zirco...

This paper presents a new physically-based deepsubmicron MOS transistors matching model that eliminates the large discrepancy between measured matching parameters and the values computed with the existing matching models. Previously neglected effects specific to the deep-submicron MOSFETs with highly doped channel and ultra-thin gate such as channel and gate random dopant fluctuation, gate depl...

Techset Com A high reliability offset-tolerant sensing circuit is presented for deep submicron spin transfer torque magnetic tunnel junction (STT-MTJ) memory. This circuit, using a triple-stage sensing operation, is able to tolerate the increased process variations as technology scales down to the deep submicron nodes, thus improving significantly the sensing margin. Meanwhile, it clamps the bi...

Capacitor-couple technique used to lower snapbacktrigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-coup...

Introduction: This paper analyses the ability of single-photon avalanche diodes (SPADs) for neural imaging. The current trend in the production of SPADs moves toward the minimumdark count rate (DCR) and maximum photon detection probability (PDP). Moreover, the jitter response which is the main measurement characteristic for the timing uncertainty is progressing. Methods: The neural imaging pro...

Scaling of feature sizes in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. This has been the driver for the revolution in communications and computing. However, questions regarding the limits of scaling (and hence Moore's Law) have arisen in recent years due to the emergence of deep submicron noise. The tutorial describes noise in deep s...

The complexity of huge-scale integrated circuits allowed by technology scaling down breeds design problems for the diÆculty in managing deep-submicron drawbacks. Thermal e ects have increasing impact on power supply bus reliability, and e ective line sizing based on trustable lifetime evaluation is of basic importance. This work presents an analysis of the impact on electromigration of technolo...

Local carrier heating and nonstationary effects in deep-submicron silicon devices can lead to substantial deviation between simulation results of classical device simulators and experimental data. A significant improvement of the physical accuracy of the simulation is achieved by adding a self-consistent solution of the carrier energy balance equation to the classical driftdiffusion set of equa...