The lazy Viterbi decoder is a maximum-likelihood decoder for block and stream convolutional codes. For many codes of practical interest, under reasonable noise conditions, the lazy decoder is much faster than the original Viterbi decoder. For a code of constraint length , the lazy algorithm is about 50% faster than an optimized implementation of the Viterbi decoder whenever SNR dB. Moreover, wh...

The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.

multi-part words in english language are hyphenated and hyphen is used to separate different parts. persian language consists of multi-part words as well. based on persian morphology, half-space character is needed to separate parts of multi-part words where in many cases people incorrectly use space character instead of half-space character. this common incorrectly use of space leads to some s...

Turbo decoding is viewed as superior alternate decoding technique in communication system, the circuit complexity and power consumption of turbo decoder implementation can often be prohibitive for power constrained system. To address these issues a power efficient turbo decoder based on soft out viterbi algorithm is designed. SOVA based turbo decoder can be implemented with high throughput and ...

The key objective of this project is to design a decoder which can be used for hardware purpose. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of m=2 output lines. In this paper are design of Dynamic decoder and Tree Decoder. Also shows a comparative analysis of tree decoder with corresponding dynamic decoder and tree decoder highlights th...

—This article presents an FPGA implementation of an ultra-high-speed Reed-Solomon (RS) turbo decoder. A performance analysis is performed showing that RS Block Turbo Codes (RS-BTC) have decoding performance equivalent to Bose Ray-Chaudhuri Hocquenghem-Block Turbo Codes (BCH-BTC). A ratio between the decoder throughput and the decoder area is used to show the higher ef ciency of the RS full para...

We propose use of QR factorization with sort and Dijkstra’s algorithm for decreasing the computational complexity of the sphere decoder that is used for ML detection of signals on the multi-antenna fading channel. QR factorization with sort decreases the complexity of searching part of the decoder with small increase in the complexity required for preprocessing part of the decoder. Dijkstra’s a...

In wireless communication, the channel state changes repeatedly. In this situation, we select the specification of the Viterbi decoder for the worst case channel state. However, if we select the specification of the Viterbi decoder with such a criterion, the decoder operates inefficiently in the good channel state. In this paper, we propose a specification controllable Viterbi decoder without u...