We describe a C compiler tailored to save space in executables. It accepts an arbitrary C program and customizes for it a compact interpreter and interpretive code. In a typical application, the compiler halves its own size. We have written programs that collaborate to compile an arbitrary C program into a compact interpreter and interpretive code. It improves on prior efforts to automatically ...

General-purpose processors that are utilized as cores are often incapable of achieving the challenging cost, performance, and power demands of high-performance audio, video, and networking applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine...

A common way of improving an application’s performance is implementing it on a custom hardware. High level synthesis (HLS) and application specific instruction-set processor are two alternatives for automating this process. HLS techniques usually can handle small programs. Also, since the datapath is not available during scheduling, limited datapath and layout optimizations (such as interconnec...

of Thesis presented to COPPE/UFRJ as a partial fulfillment of the requirements for the degree of Doctor of Science (D.Sc.) AUTOMATIC COMPLEX INSTRUCTION IDENTIFICATION WITH HARDWARE SHARING FOR EFFICIENT APPLICATION MAPPING ONTO ASIPS Alexandre Solon Nery December/2014 Advisors: Felipe Maia Galvão França Nadia Nedjah Lech Jóźwiak Henk Corporaal Department: Systems Engineering and Computer Scien...

As increasing the clock frequency leads to unmanageable heat and power dissipation the search is on for another way to get more power efficient and faster embedded systems. Given that chip area is also a constraint, we investigate the addition of a custom instruction to the processor instruction set which enables the execution of an efficient complex division. We have implemented software for c...

This paper describes an approach for adaptive dynamic instruction set extension, tuning processors to specific applications. These new instructions are generated after production. The processor has two modes: training mode and normal mode. The application-specific instructions are extracted from the critical portions of the code detected by a profiler at training mode. At normal mode they are e...

1383-7621/$ see front matter 2008 Elsevier B.V. A doi:10.1016/j.sysarc.2008.06.003 * Corresponding author. Tel.: +65 67906643; fax: + E-mail addresses: [email protected] (S.K. L (T. Srikanthan). RISPs (Reconfigurable Instruction Set Processors) are increasingly becoming popular as they can be customized to meet design constraints. However, existing instruction set customization methodologies d...

Reconfigurable instruction set processors allow customization for an application domain by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an application on a reconfigurable instruction set processor. A custom instruction (CI) is usually extracted from critical portions of applications and implemented on a reconf...