This paper focuses on two desired properties of cell-based switches for digital data networks: (1) data cells should not be detained inside the switch any longer than necessary (the work-conserving property) and (2) data cells that have been in the switch longer (older cells) should have priority over younger cells (the order-conserving property). A well-known, but expensive design of a workand...

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohib...

Tremendous amounts of effort have gone into research on switch designs and architectures. This survey attempts to sketch the evolution of the modern switch architectures. The survey covers the literature over the period 1987-2008 on switch architectures. Starting with the simple crossbar switch, we explore various architectures such as Output queueing, Input queueing, Combined Input/Output queu...

The crossbar is very popular for the implementation of switches with a moderate number of ports. Unbuffered crossbars (IQ architecture) require complex switch matrix scheduling algorithms that operate on fixed-size cells. On the other hand, buffered crossbars (CICQ architecture), use small buffers at the crosspoints and provide excellent features; scheduling is simplified and variable-size pack...

The amount of memory in buffered crossbars in combined input-crosspoint buffered switches is proportional to the number of crosspoints, or O(N), where N is the number of ports, and to the crosspoint buffer size, which is defined by the distance between the line cards and the buffered crossbar, to achieve 100% throughput under high-speed data flows. A long distance between these two components c...

In this paper, we propose a continuous hysteresis neurons (CHN) Hopfield neural network architecture for efficiently solving crossbar switch problems. A Hopfield neural network architecture with continuous hysteresis and its collective computational properties are studied. It is proved theoretically and confirmed by simulating the randomly generated Hopfield neural network with CHN. The network...

In this paper, we propose a continuous hysteresis neurons Hopfield neural network architecture for efficiently solving crossbar switch problems. A Hopfield neural network architecture with continuous hysteresis and its collective computational properties are studied. It is proved theoretically and confirmed by simulating the randomly generated Hopfield neural network with continuous hysteresis ...

This paper describes a crossbar-switch arbiter for a high-speed MAPOS switch. The arbiter uses the following techniques suitable for variable-length frame switching: 1. parallel processing for handling requests from network interfaces and for resource allocation, 2. techniques such as release-on-request, fast back-to-back transfer, and request prefetching to reduce the arbitration overhead, and...