The design and analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation. Simulation results are obtained in 0.18um with supply voltages of 1....

: This paper presents a high speed current mode CMOS comparator. The comparator was optimized for allows wide range input current 1mA, ±0.5uA resolution and has fast response. This circuit was implemented with 0.8μm CMOS nwell process with area of 120μm X 105μm and operates with 3.3V (±1.65V).

In high speed ADC, speed limiting element is comparator. This paper describes a very high speed and low offset preamplifierlatch comparator. The threshold and width of the new comparator can be reduced to the mV range, the resolution and the dynamic characteristics are good. Based on TSMC 0.18um CMOS process model, simulated results show the comparator can work under ultra high speed clock freq...

A new double tail parallel latch load comparator are compared in term of voltage,power,delay and offset voltage.CMOS dynamic comparator which has dual input, dual output inverter stage suitable for high speed analog-to-digital converters with low voltage and low power. A single tail comparator is replaced with a double tail dynamic comparator which reduces the power and voltage by increasing th...

We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 2.5-bit to 7.05-bit. The ADC is manufactured in a 90 nm CMOS technology, with a core area of 0.85 mm 9 0.3...

High-speed tree-based 64-bit binary comparator: A New Approach is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concent...

Version 1, October 1, 2006 A methodology for determining the input referred offset voltage of comparators is presented. This in general is difficult as the output of a comparator is discrete valued. The method relies on a Monte-Carlo-Simulation with certain comparator input values and some postprocessing of the comparator output data. The comparator is always operated in its intended environmen...

A high-speed tree-based 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on...

High-speed 64-bit binary comparator using two stages with two different logic styles is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comp...