This paper proposes a low power CMOS operational amplifier which operates at 1.8 V power supply. The unique behavior of the MOS transistors in sub-threshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Designing of two-stage Op-Amp is a multi-...

In this research paper, Simulation and Analysis of innovative folded cascode Operational Amplifier based on carbon nanotubes (CNT) has been performed using 45 nm technology. DC voltage gain, average power, bandwidth and output resistance have been computed. CNT based folded cascode Op Amp results in high performance with the increase of CNTs. For example, the increase in DC gain is 41.48% in pC...

In this contribution, a highly efficient CMOS based operational amplifier has been presented that uses the circuit arrangement so as to provide an extra bias current into a conventional CMOS differential input signal which is required for high performance of the system. The design of a high performance CMOS operational amplifier (op-amp) with level 3 parameters at 0.2ìm CMOS technology, that ma...

This paper presents the application of reinforcement learning in automatic analog IC design. In this work, the Multi-Objective approach by Learning Automata is evaluated for accommodating required functionalities and performance specifications considering optimal minimizing of MOSFETs area and power consumption for two famous CMOS op-amps. The results show the ability of the proposed method to ...

A new circuit technique for voltage gain enhancement in CMOS op amp design suitable for low voltage and high speed operation is presented in this paper. A negative conductance is used to cancel the positive output conductance of an amplifier thereby reducing the total equivalent output conductance and increasing the voltage gain of the amplifier. The negative conductance is derived from the out...

A frequency compensation technique for the improvement of unity gain bandwidth (UGB) and power supply rejection ratio (PSRR) of two stage operational amplifiers is presented in this paper. Performance of proposed op-amp is compared with classical miller compensated op-amp and op-amp proposed by G. Blakiewicz [13]. The technique exploits the triode mode operation of a MOSFET in the compensation ...

The operational amplifier is perhaps the most useful integrated device in existence today. It is widely used in analogue computers, simulation systems and in a variety of electronic applications such as filtering, buffering and comparison of signal levels. In this paper, the different schemes of power-efficient class AB two-stage op-amps using a current replication branch and adaptive loads wer...

In this paper the challenge of enhancing the gain and reducing the power requirement of amplifiers, preferably used in biomedical applications is addressed by demonstrating that composite cascode stages, operating in subthreshold/weak inversion regions provide a method of designing a ultra high gain (97dB) and low-power (21μW) op amp with 1.5V power supply. The op amp is designed without compen...

In this paper, CMOS Sample-and-Hold (S/H) is presented. The S/H circuit is an important component in Analog-to-digital Converter (ADC). In low frequency application, the boost clock technique is used to constitute a rail-to-rail signal voltage with low distortion. The operational amplifier works as a unity gain buffer in the S/H circuit. However, a two-stage op-amp is proposed with enhanced low...

This paper describes a single op-amp 0+2 ⌃ architecture and design considerations to achieve 12-b resolution on a 2-MHz bandwidth. The proposed topology combines op-amp reduction and MASH techniques. In particular, the second-order ⌃ stage uses direct synthesis of the noise transfer function (NTF) and employs only one op-amp. The use of multi-bit quantization on both stages increases the resolu...