A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

Based on the Grossberg mathematical model called the outstar, a modular neural net with on-chip learning and memory is designed and analyzed. The outstar is the minimal anatomy that can interpret the classical conditioning or associative memory. It can also be served as a general-purpose pattern learning device. To realize the outstar, CMOS (complimentary metal-oxide semiconductor) current-mode...

The new emerging non-volatile memory (NVM) devices known as memristors could be the promising candidate for future digital architecture, owing to their nanoscale size and its ability integrate with existing CMOS technology. device has involved in various applications from design analog circuit design. In this paper, a combination of memristor transistors is working together form hybrid CMOS-mem...

Abstract  In his paper a new current-controlled conveyor (CCCII) in CMOS technology is presented. It features, low supply voltage (±0.7), low power consumption, low circuit complexity, rail to rail operation and wide range parasitic resistance ( ). The circuit has been successfully employed in a multifunction biquad filter. Simulation results by HSPICE show high performance of the circuit and c...

Hybrid integration of CMOS and nonvolatile memory (NVM) devices has become the technology foundation for emerging nonvolatile memory based computing. The primary challenge to validate a hybrid memory system with both CMOS and nonvolatile devices is to develop a SPICE-like simulator that can simulate the dynamic behavior accurately and efficiently. Since memristor, spin-transfer-toque magnetic-t...

This paper describes the defect coverage evaluation of memory testing algorithms. Realistic CMOS defects were extracted from a 2 2 SRAM layout using an IFA tool, and circuit simulations were performed to measure the defect coverages of the eleven memory testing algo-

defuzzifier circuit is one of the most important parts of fuzzy logic controllers that determine the output accuracy. the center of gravity method (cog) is one of the most accurate methods that so far been presented for defuzzification. in this paper, a simple algorithm is presented to generate triangular output membership functions in the mamdani method using the multiplier/divider circuit and...

this paper presents a design of an uwb downconversion integrated cmos resistive ring mixer with linear voltage regulator (lvr), to supply required biasing voltages for the mixer section. the designed mixer circuit has been optimized for using in heart rate extraction system with microwave doppler radar at 2.4ghz frequency. this mixer needs 2 dc bias voltages equal to 0.5 and 1 volts for its bes...

Cognitive radio and/or SDR (Software Defined Radio) inherently requires multi-band and multi standard wireless circuit. The circuit is implemented based on Si CMOS technology. In this article, the recent progress of Si RF CMOS is described and the reconfigurable RF CMOS circuit which was proposed by the authors is introduced. At the present and in the future, several kind of Si CMOS technology ...

Spin-torque-transfer (STT) magnetoresistive random-access memory (MRAM) [1-3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access. However, two circuit-level challenges remain for STT-MRAM: potentially destructive read access due to device variation and a high-power write a...