This paper presents a 5-Gb/s low-power burst-mode clock and data recovery circuit based on analog phase interpolator for passive optical network applications. The proposed clock recovery unit consists of two double-edge triggered sample-and-holds (DTSHs) and a phase interpolator. The PI instantaneously locks the recovered clock to incoming burst-mode data by coefficients generated at the DT-SHs...

This paper describes a 1.25-Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700MHz bandwidth for 1pF photodiode capacitance, 80dBΩ transimpedance gain, -17dBm sensitivity for BER of 10-12, a...

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recove...

A 4Gb/s power and area efficient clock/data recovery (CDR) circuit is proposed. Fully-differential design is employed to reject any common mode noises and to significantly reduce power/ground bounce. An analog dual delay-locked loop (DLL) architecture continuously aligns the clock sampling edge to the center of incoming data eye-opening. A self-correcting function prevents the phase capture ran...

A 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial link without the reference clock is described. The CDR has a phase and frequency detector (PD and FD), which incorporates a half-rate bang-bang type oversampling PD and a half-rate frequency detector that can achieve low-jitter operation and improve pull-in range. The PD of oversamping method finds a phase error by generati...

A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy. (August 2009) Hyung-Joon Jeon, B.S., Seoul National University Chair of Advisory Committee: Dr. Jose Silva-Martinez As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited chann...

High Speed Clock and Data Recovery Techniques Behrooz Abiri Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto 2011 This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this...

We present and evaluate a compact, all-optical Clock and Data Recovery (CDR) circuit based on integrated Mach Zehnder interferometric switches. Successful operation for short packet-mode traffic of variable length and phase alignment is demonstrated. The acquired clock signal rises within 2 bits and decays within 15 bits, irrespective of packet length and phase. Error-free operation is demonstr...

This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and temperature (PVT) variations and to increase the lock range, a frequency locked loop is ...