Branch misprediction limits processor performance signiWcantly, as the pipeline deepens and the instruction issued per cycle increases. Since the introduction of the two-level adaptive branch predictor, branch history has been a major input vector in branch prediction, together with the address of a branch instruction. Until now, the length of branch history has been statically Wxed for all bra...

Branch prediction is an important mechanism in modern microprocessor design. The focus of research in this area has been on designing new branch prediction schemes. In contrast, very few studies address the inherent limit of predictability of program themselves. Programs have an inherent limit of predictability due to the randomness of input data. Knowing the limit helps us to evaluate how good...

Low-power design has gained much attention recently, especially for computing on batterypowered equipments. Reducing BTB (branch target buffer) accesses is an effective way to reduce processor power consumption, since BTB consumes a significant portion of power in a processor. In this paper, we propose two approaches to reduce BTB accesses. The first approach expects the distance of every two d...

Historically, Markovian predictors have been very successful in predicting branch outcomes. In this work we propose a hybrid scheme that employs two Prediction by Partial Matching (PPM) Markovian predictors, one that predicts based on local branch histories and one based on global branch histories. The two independent predictions are combined using a neural network. On the CBP-2 traces the prop...

Energy efficiency is of the utmost importance in modern high-performance em-bedded processor design. As the number of transistors on a chip continues to in-crease each year, and processor logic becomes ever more complex, the dynamicswitching power cost of running such processors increases. The continual progres-sion in fabrication processes brings a reduction in the feature size...

We propose novel power efficient branch predictors for the Cell SPU, which normally depends on compiler inserted hint instructions to predict taken branches. Several prediction schemes were designed all using a Branch Target Buffer (BTB) to store the branch target address and the prediction, which is computed using a bimodal counter. One prediction scheme pre-decodes instructions once they are ...

The new neural predictor improves accuracy by combining path and pattern history to overcome limitation inherent to previous predictors. It uses a different prediction algorithm that would allow parallel execution of instructions during every prediction, thereby keeping the latency low. In fact, the fast path-based neural predictor has a latency comparable to the predictors from industrial desi...

Simultaneous multithreading (SMT) provides significant increases in microprocessor throughput by issuing instructions from multiple threads per clock cycle. SMT can be realized in a wide-issue superscalar with a modest increase in resources, because much of the hardware is shared among the multiple thread contexts. Branch prediction accuracy, a key component of microprocessor performance, can s...