This paper gives important features of CMOS and BiCMOS four-diodes direct coupled tuneable resistance. Circuit performances of three resistance topologies are explored and compared with the traditional CMOS tuneable transresistance designed from a one-stage operational transconductance amplifier (OTA). Simulations results have been realised using nominal parameters of the AMS 0.8μm CMOS and BiC...

This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where a...

Logic Behavior of Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

A true single-phase clock BiCMOS latch intended for the use in high-performance deeply pipelined digital systems is proposed. It is based on quasi-complementary BiCMOS circuit, and uses single-phase clock. The speed and power performance of this latch are superior to previously published results, which has been shown by simulation in 0.8μm technology.

In deep submicron CMOS and BICMOS technologies, antenna effects affect floating gate charge of usual floating gate test structures, dedicated to capacitor matching measurement. In this paper a new pseudo-floating gate test structure is designed. After test structure and modeling presentation, testing method and results are given for several capacitor layouts (poly-poly and metal-metal). key wor...

The limitations on the implementation of BiCMOS active inductors at 2GHz are described. The circuit is based on a two BJT feedback configuration. Two types of biasing circuits were used: active bias and resistive bias. With 0.8μm BiCMOS standard technology is possible to obtain up to a few nanohenry inductance with a Q close to 3 at 2GHz. Two MMIC were studied.

The performance enhancement of a SiGe:C HBT for RF/IF applications is described for Motorola’s 0.35μm and 0.18μm BiCMOS technologies. Cutoff frequencies (fT) have been improved from 50GHz to 78/84GHz (0.35/0.18μm BiCMOS), with a reduction in minimum noise figure (NF) from 0.7dB to 0.3dB. Improvements occurred through the optimization of the intrinsic collector and base dopant profiles, extrinsi...

New true single-phase clock (TSPC) BiCMOS circuits are described. The TSPC latches are intended for use in highperformance deeply pipelined digital electronic systems. The circuits described are based on quasi-complementary BiCMOS circuit using single-phase clock. They are verified to have fullswing operation with supply voltages as low as 1.5V. The speed and power performance of the new latch ...

IBM Microelectronics Division, Essex Junction, VT, [email protected] *Ericsson Mobile Platforms AB, Nya Vattentornet, SE-221 83 Lund, Sweden, [email protected] **IBM Microelectronics Division, East Fishkill, NY We present for the first time a fully-manufacturable 0.5μm/3.3V SiGe BiCMOS technology that supports multiple mode (GSM/ PCS/ WCDMA) power amplifier applications, highlighting H...

In this paper we propose a new low-noise low voltage BiCMOS instrumentation amplifier (IA) with high CMRR and exempted from resistance matching. This IA is dedicated to nerve signal recording as a part of implantable prostheses. The IA design and the simulation with the BiCMOS 0.8 μm technology are presented .The gain is programmable by using a network of resistors. The IA features a common-mod...