Distributed Video Coding (DVC), one of the most active research field in the video coding community, is based on the combination of Slepian-Wolf coding techniques with the idea of performing the prediction at the decoder side rather than at the encoder side. Besides its main property, which is flexible allocation of computational complexity between encoder and decoder, the distributed approach ...

—This article presents an FPGA implementation of an ultra-high-speed Reed-Solomon (RS) turbo decoder. A performance analysis is performed showing that RS Block Turbo Codes (RS-BTC) have decoding performance equivalent to Bose Ray-Chaudhuri Hocquenghem-Block Turbo Codes (BCH-BTC). A ratio between the decoder throughput and the decoder area is used to show the higher ef ciency of the RS full para...

This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its highspeed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipe...

The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.

To achieve the high data rate requirements of emerging wireless communication technologies, the iterative turbo decoding architecture have been proposed and it requires the use of parallel architectures to implement high throughput Turbo decoder. Turbo decoder consists of SISO decoder, LDPC Decoder, interleaver and deinterleaver. Contention-free Unified parallel Confection and balance schedulin...