111 this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset arid imniediate operands can be extended to 32 bits via the operat...

The Blackfin Handy Board is a new robot controller inspired by the original MIT Handy Board. The Blackfin Handy Board was developed in collaboration with Analog Devices, Inc., and is based on their Blackfin DSP chip, which combines a 16-bit integer DSP engine with a 32-bit RISC CPU. This paper provides an overview of the architecture of the Blackfin Handy Board, including the hardware design an...

Today’s mobile processors must often times tackle a multitude of computing applications, many of which do not require the full 32-bit data word for their computations. In light of this, it is possible to restrict the computations for these applications to a reduced width data word to minimize power consumption. A modification to a standard RISC architecture is presented to reduce the overall po...

In this paper, we propose a guess and determine attack against some variants of the π-Cipher family of authenticated ciphers. This family of ciphers is a second-round candidate of the CAESAR competition. More precisely, we show a key recovery attack with time complexity little higher than 2, and low data complexity, against variants of the cipher with ω-bit words, when the internal permutation ...

An efficient algorithm derived from AAN algorithm (proposed by Arai, Agui, and Nakajima in 1988) for computing the Inverse Discrete Cosine Transform (IDCT) is presented. We replace the multiplications in conventional AAN algorithm with additions and shifts to realize the fixed-point and multiplier-free computation of IDCT and adopt coefficient and compensation matrices to improve the precision ...

Figure 1 is a block diagram representation of the I/O and architecture for a 16 or 32-bit counter. Pin CLK is the clock signal, RST the reset signal, and LOAD the load data signal. CLK is a positive, edge-triggered synchronous signal, and LOAD is an active low, synchronous signal. Pins D0 through D15, 31 are the load data inputs, and pins Q0 through Q15, 31 are the count bits. Pin Ci is the car...