We designed a VLSI chip of FFT multiplier based on simple Cooly Tukey FFT using a floating-point representation with optimal data length based on an experimental error analysis. The VLSI implementation using HITACHI CMOS 0.18μm technology can perform multiplication of 2 to 2 digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFT multiplier at an area cost ...

In this work, an FFT architecture supporting variable FFT sizes, 128∼2048/1536, is proposed. This implementation is a combination of a 2 point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase t...

This paper introduces a kind of FFT algorithm design and realization based on the Xilinx IP core . On the analysis of FFT algorithm, Rely on Xilinx Spartan -3A DSP FPGA series as platform, by calling FFT IP core, validating the feasibility and reliability in FFT algorithm medium or lower end FPGA. Keywords-FFT algorithm module, Xilinx IP core, Spartan 3A DSP, Fixed-point compression

Beamforming methods using antenna arrays have been used to suppress co-channel interferences in OFDM systems. These methods are grouped into two general classes of pre-FFT and post-FFT schemes. Post-FFT schemes normally exhibit better performance than their pre-FFT counterparts. However, in pilot-assisted OFDM systems the performance of post-FFT schemes drastically degrades due to subcarrier cl...

The numerical calculation of the Rayleigh-Sommerfeld diffraction integral is investigated. The implementation of a fast-Fourier-transform (FFT) based direct integration (FFT-DI) method is presented, and Simpson's rule is used to improve the calculation accuracy. The sampling interval, the size of the computation window, and their influence on numerical accuracy and on computational complexity a...

A novel architecture FFT processor which can carry on 1-D FFT algorithm or 2-D FFT algorithm corresponding different size of FFT is proposed in this paper. The architecture is served as a scalable IP Core which is suitable for the heterogeneous multi-core SoC on chip application. The mixed architecture FFT processor achieves balance between high processing speed and resources. Compared with a c...

The FFT processor is a very important component in Orthogonal Frequency Division Multiplexing(OFDM) communication system. In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. The pipelined radix-8/4/2 butterfly unit computes radix-8 FFT algor...

The Fast Fourier Transform (FFT) is widely used in various digital signal processing applications. The performance requirements for FFT in modern real-time applications has increased dramatically due to the high demand on capacity and performance of modern telecommunication systems, where FFT plays a major role. Software implementations of FFT running on a general purpose computer can no longer...

Fructans are the main storage compound in Lolium perenne. To account for the prevailing neokestose-based fructan synthesis in this species, a cDNA library of L. perenne was screened by using the onion (Allium cepa) fructan:fructan 6G-fructosyltransferase (6G-FFT) as a probe. A full length Lp6G-FFT clone was isolated with significant homologies to vacuolar type fructosyltransferases and invertas...

an important section of range-doppler imaging algorithm in sar systems which needs large number of resources, memories and solution time, is fft on the azimuth dimension. in this paper, by decomposing the fft relation, and converting to smaller dimension ffts, implementation has been simplified. the proposed method, based on removing the extra phase factors reduces the resources, memories and s...