نتایج جستجو برای: ترانزیستور finfet

تعداد نتایج: 1014  

2016
Mehdi Saremi Ali Afzali-Kusha Saeed Mohammadi

In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL). To assess the performance of the proposed structure, some device characteristics of the structure have been compared ...

2013
Cheng-Hsien Chang Hung-Pei Hsu Chan-Hsiang Chang Ming-Tsung Shih Shih-Chuan Tseng

In this paper, we have proposed a novel FinFET with extended body under the poly gate, which is called EB-FinFET, and its characteristic is demonstrated by using three-dimensional (3-D) numerical simulation. We have analyzed and compared it with conventional FinFET. The extended body height dependence on the drain induced barrier lowering (DIBL) and subthreshold swing (S.S) have been also inves...

2015
Anshul Jain

Scaling of gadgets in mass CMOS engineering helps short direct impacts and increment in spillage. Static arbitrary access memory (SRAM) is required to involve 90% of the zone of Soc. Since spillage turns into the essential variable in SRAM cell, it is actualized utilizing FinFet. FinFet gadgets got to be better option for profound submicron advances. In this paper, 6t SRAM cell is actualized ut...

2015
S. Priyanka P. Deepa V. M. Senthil Kumar

Scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic.CMOS devices are shrinking to nanometer regime, increasing the consequences in short channel effects and variations in the process parameters which lead to cause the reliability of the circu it as well as performance. To solve t...

یک فشرده ساز، بلوک سازنده بسیاری از مدارات محاسباتی می‌باشد. طراحی یک فشرده ساز که مساحت کوچکتر، توان مصرفی کم و سرعت بالا دارد همواره مورد تقاضا می‌باشد. از آنجاییکه طول کانال به سمت مقیاس نانو میل می‌کند استفاده از MOSFET به عنوان افزاره پایه در فشرده‌ساز اکنون به محدودیت های عملکردی خود از قبیل اتلاف توان میانگین و سرعت نائل می‌شود. در این مقاله، یک سلول تمام جمع کننده یک بیتی با استفاده از ...

2011
Gaurav Saini Ashwani K Rana

In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-le...

2012
Samson Mil’shtein Lalitha Devarakonda Brian Zanchi John Palma

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the ...

2015
Ahmed Yahya Morsy

Abstract— FinFet is evolved to overcome Moore's law limitations in nanometer regime. Transconductance circuit produces differential output currents, when differential input voltages are applied. A simple FinFet transconductance circuit structure modified from traditional MOSFET is proposed to preserve both area and power. The proposed design contributes a transconductance gain of 5.247 mA/v for...

2015
Kanika Mishra Ravinder Singh Sawhney Scott E. Thompson Srivatsan Parthasarathy Gordon E. Moore J. P. Colinge Bin Yu Leland Chang Shibly Ahmed Haihong Wang Scott Bell Chih-Yuh Yang Cyrus Tabery Chau Ho Qi Xiang Tsu-Jae King Jeffrey Bokor Chenming Hu Ming-Ren Lin David Kyser A. Mercha B. Parvais J. Loo C. Gustin M. Dehan N. Collaert M. Jurczak G. Groeseneken Flavia Princess Nesamani Geethanjali Raveendran Lakshmi Prabha Wen-Chin Lee Jakub Kedzierski Hideki Takeuchi Kazuya Asano Charles Kuo Erik Anderson S. L. Tripathi

A double gate FinFET can reduce drain induced barrier lowering and improve threshold (short channel effects). In this paper, a very important geometrical parameter, that is, the fin width of a FinFET has been analyzed. In this article, a double gate n channel FinFET with a gate length of 20nm has been reported. The transfer characteristics of the FinFET at various fin widths have been obtained ...

2016
Anthony S. Oates

INTRODUCTION For technology scaling beyond 20 nm, FinFET transistors will replace the conventional planar geometry. The driving force for the introduction of FinFET architecture is the superior immunity to short-channel effects and the reduction of the effects of process variation on device performance exhibited by the FinFET.[1-4] Figure 1 shows a comparison of architectures of the planar FET ...

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