Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for struc...

In this paper, we present an evolutionary algorithm application to partitioning VLSI circuits on subcircuits with minimal number of connections between them. The algorithm is characterized by a multi-layer chromosome structure. Due to this structure, the partition of circuits is possible without applying a repair mechanism in the algorithm. The test circuits chosen from literature and created r...

Integrated Systems Group is focused on several key design aspects of modern integrated systems. The group is focused on building cutting edge, energy-efficient integrated systems through vertical optimization encompassing communications and signal processing algorithms and architectures, and digital and mixed-signal circuits. The main research topics include modeling of noise and dynamics in ci...

In recent years, there have been major advances in integrated circuit technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signal. Such circuits, called multiple-valued logic circuits, offer several potential opportunities for the improvement of present VLSI circuit designs. In this paper, we give an overview ...

As technology advances to giga-scale integration level, global interconnect resource becomes increasingly valuable in a VLSI chip. This is due to the exponential growth of the total number of interconnects/wires as the feature size of MOS transistors decreases in scaled deep submicron CMOS technologies. Interconnect length, however, has not scaled down with feature size and remains long relativ...

The interwire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called crosstalk constraints, are usually given in the design speci...

Semistate theory as applied to electronic circuits is reviewed in a tutorial fashion. The resulting theory is applied to the design of linear vlsi circuits using an admittance framework for which the main components are CMOS capacitors, differential pairs and current mirrors. The results are extended to nonlinear designs through the use of CMOS multipliers. by Angela M. Hodge and Robert W. Newcomb

In this paper, we propose a technique that utilizes the genetic algorithm for various VLSI circuits. In GA, we proposed the method of automatic test pattern generation (ATPG) is used to generate test vectors. Experiment results showed that the proposed algorithm reduce the complexity of the circuits and also the execution time. The design is realized using VHDL and then fabricated on FPGA.

Integrated Systems Group is focused on several key design aspects of modern integrated systems. The group is focused on building cutting edge, energy-efficient integrated systems through vertical optimization encompassing communications and signal processing algorithms and architectures, and digital and mixed-signal circuits. The main research topics include modeling of noise and dynamics in ci...

| The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called cross-talk constraints, are usually given in the design s...