| Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for twolayer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

Paschalis et al. in [12] have given a structured method to design TSC m-out-of-2m code checkers suitable for VLSI implementation. In this correspondence we give sufficient conditions so that the method given in [12] can be used to design checkers for classes of m-outof-n codes with n * 2m.

In order to achieve multi-GHz operation frequency for VLSI design, clock networks need to be designed in a very elaborated manner and be able to deliver prescribed useful skews rather than merely zero-skew. Although traditional zero-skew clock routing methods can be extended directly to prescribed skews, they tend to result in excessive wirelength as the differences among delay-targets for cloc...

The field of neuromorphic engineering is a relatively new one. In this paper we introduce the basic concepts underlying neuromorphic engineering and point out how this type of research could be exploited for industrial applications. We describe some of the circuits commonly used in neuromorphic analog VLSI chips and present examples of neuromorphic systems, containing vision chips for extractin...

This paper describes a new algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of large IC’s and non-Manhattan geometry. Concept of the contact/via contacting regions is proposed and its relevance is discussed. Illustrative examples of the proposed algorithm are presented.

The problem of ordering and sizing parallel wires residing in a single metal layer within an interconnect channel is addressed in this paper. Wires are ordered such that cross-capacitances between neighboring wires are optimally shared for circuit delay minimization. Using an Elmore delay model including cross capacitances, an optimal wire ordering is uniquely determined, such that average sign...