An important assumption for many KA researchers is structure preservation ; i.e. conceptual models can be converted in a straight forward manner into a design for an implementation. This assumption may not always hold. Seemingly trivial variants in a qualitative conceptual models can block pragmatically desirable properties such as KB-testability and KB-maintainability. KB-testability and KB-ma...

Dr. Jeffrey Voas has published more than 150 journal and conference papers in the areas of software testability, software reliability, debugging, safety, fault-tolerance, design, computer security and career management. Jeff is widely recognized as a pioneer in both applying practical solutions for measuring software testability and inventing novel applications for software fault injection meth...

A methodology for modifying VHDL descriptions is the core of this paper. Modifications are performed on general RTL descriptions composed of a mix of control and computation, that is, the typical type of description used for designing at the RT level. Such VHDL descriptions are automatically partitioned into a reference model composed of a controller driving a data-path. We call this transforma...

Abstract—Testability modeling is a commonly used method in testability design and analysis of system. A dependency matrix will be obtained from testability modeling, and we will give a quantitative evaluation about fault detection and isolation. Based on the dependency matrix, we can obtain the diagnosis tree. The tree provides the procedures of the fault detection and isolation. But the depend...

In this paper, we present TAO, a novel methodology for highlevel testability analysis and optimization of register-transfer level controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circui...

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various faul...

PURPOSE To compare testability of vision and eye tests in an examination protocol of 9- to 17-year-old patients with autism spectrum disorder (ASD) to typically developing (TD) peers. METHODS In a prospective pilot study, 61 children and adolescents (34 with ASD and 27 who were TD) aged 9 to 17 years completed an eye examination protocol including tests of visual acuity, refraction, convergen...

It is well known that the tests and diagnostics influence greatly the communication software reliability. The testability and the easiness of the diagnostic process of communication software are becoming a major concern of the design community. The fault detection and the fault localization problems are strongly related issues. The easiness of diagnostics can be seen as a criteria of testabilit...

In this paper a novel hierarchical DfT methodology is presented which is targeted to improve the delay fault testability for external testing and scanbased BIST. After the partitioning of the design into high frequency macros, the analysis for delay fault testability already starts in parallel with the implementation at the macro level. A specification is generated for each macro that defines t...

The testing properties of a class of regular circuits called convergent trees are investigated. Convergent trees include such practical circuits as comparators, multiplexers, and carry-lookahead adders. The conditions for the testability of these tree circuits are derived for a functional fault model. The notion of L-testability is introduced, where the number of tests for a plevel tree is dire...