Random number generation is a fundamental security primitive for RFID devices. However, even this relatively simple requirement is beyond the capacity of today’s average RFID tag. A recently proposed solution, Fingerprint Extraction and Random Number Generation in SRAM (FERNS) [14,15], involves the use of onboard RAM as the source of “true” randomness. Unfortunately, practical considerations pr...

Nowadays, reducing memory energy has become one of the top priorities of many embedded systems designers. Given the power, cost, performance and real-time advantages of Scratch-Pad Memories (SPMs), it is not surprising that SPM is becoming a common form of SRAM in embedded processors today. In this paper, we focus on heuristic methods for SPMs careful management in order to reduce memory energy...

In this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to improve the write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the SRAM cell while another bitline is connected to a boosted voltage. Improved write features are attributed to the boosting scheme from both sides of the SRAM cell. This technique is applied to a 10T...

Using a newly introduced alternative to a conventional SRAM cell a binary zero can be written with a much lower power consumption than a binary one. Such a solution reduces power consumption, especially if there are few ones in the data, that is, if the data has a low Hamming weight. If the data is not inherently of low weight, this can be achieved by encoding the data. In the paper such coding...

Limited memory bandwidth is a critical bottleneck in modern systems. 3D-stacked DRAM enables higher bandwidth by leveraging wider Through-Silicon-Via (TSV) channels, but today’s systems cannot fully exploit them due to the limited internal bandwidth of DRAM. DRAM reads a whole row simultaneously from the cell array to a row buffer, but can transfer only a fraction of the data from the row buffe...

Linked Faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design a very complex task. Although several March Tests have been developed for the wide memory faults spread, a few of them are able to detect linked faults. In the present paper March AB, a March Test t...

In this paper, we explore novel schemes for reducing power consumption in modern enterprise level routers and evaluate their effectiveness in terms of energy saved and impact on router performance. The largest consumers of power within routers are memory, the two biggest culprits being TCAMs and SRAM buffers. Our hardware mechanisms target the TCAM as a potential location to reduce power consum...