In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose closed-loop ada...

On chip cache memories contributes a large fraction to the total power consumption of microprocessor. As technology scales down into d e e p -submicron, leakage power is becoming a dominant source of power consumption. As cache memory is an array structure leakage reduction in just one memory cell can on the whole reduce a large amount of leakage power. In this thesis leakage power of conventio...

Spin-Transfer Torque Magnetoresistive RAM (STTMRAM) is being intensively explored as a promising on-chip last-level cache (LLC) replacement for SRAM, thanks to its low leakage power and high storage capacity. However, the write penalties imposed by STT-MRAM challenges its incarnation as a successful LLC by deteriorating its performance and energy efficiency. This write performance characteristi...

Recent advances in the development of image watermarking algorithms had made a rapid change in the authenticated information resource sharing. Among all techniques of image watermarking and storing watermarked image bits in SRAM (Static Random Access Memory), LFSR (Linear Feedback Shift Register) based image watermarking technique has been proposed in [1], this technique utilizes less design co...

Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming...

Physically unclonable functions (PUFs) have been touted for their inherent resistance to invasive attacks and low cost in providing a hardware root of trust for various security applications. SRAM PUFs in particular are popular in industry for key/ID generation. Due to intrinsic process variations, SRAM cells, ideally, tend to have the same start-up behavior. SRAM PUFs exploit this start-up beh...

As technology is scaled down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 45nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs eff...

As the technology scales down to 90 nm and below, static random access memory (SRAM) standby leakage power is becoming one of the most critical concerns for low power applications. In this article, we review three major leakage current components of SRAM cells and also discuss some of the leakage current reduction techniques including body biasing, source biasing, dynamic VDD, negative word lin...

The Internet of Things (IoT) is becoming increasingly popular in areas like wearable communication devices, biomedical and home automation systems. IoT-compatible processors or devices need larger integrated memory circuits, static random access (SRAM). design such a with fast times low leakage challenge. In this article, we have proposed 7T SRAM cell using an InGaAs-dual pocket-dual gate-tunne...

Memories Precharge-Free, Low-Power Content-Addressable Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Zackriya V and H. M. Kittur 2614 A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....