Short Abstract Most industrial digital circuits contain three-state elements besides pure logic gates. We like to presents a gate delay fault test generator for sequential circuits with standard scan design that can handle three-state elements like bus drivers, transmission gates and pulled busses. The delay test pattern generator is based on a well-proved stuck-at test pattern generator that w...

With the continuous increase of the integration densities and complexities, the problem of testing integrated circuits has become much more acute and needs an economic solution with reliable performance. This paper presents the design of a TESTCHIP implementing a multiple polynomial, multiple seed based mixed-mode test technique. Fault simulation experiments on benchmark circuits show that the ...

Retiming is a technique for optimizing sequential circuits. It repositions the registers in a circuit leaving the combinational cells untouched. The objective of retiming is to nd a circuit with the minimum number of registers for a speci ed clock period. More than ten years have elapsed since Leiserson and Saxe rst presented a theoretical formulation to solve this problem for single-clock edge...

This paper reports on the progress made in developing techniques for the verification of an occam to FPGA compiler. The compiler converts occam 1 programs into logic circuits that are suitable for loading into field-programmable gate arrays (FPGAs). Several levels of abstraction of these circuits provide links to conventional hardware implementations. Communicating Sequential Processes (CSP) ha...

Abstract— Sequential circuits are the important components of a computer system as they process binary data and buffers binary output for the next period.. Sequential circuits are the interconnection of logic gates and Flip Flops and the buffering of binary output for the next period is carried out by the Flip Flops by their inherent feedback mechanism. Sequential circuits basically process bin...