This paper describes a 1.25-Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700MHz bandwidth for 1pF photodiode capacitance, 80dBΩ transimpedance gain, -17dBm sensitivity for BER of 10-12, a...

The design of a 3.0-7.5 GHz UWB CMOS power amplifier (PA) for group 1~3 MB-OFDM UWB applications in TSMC 0.18-μm CMOS technology is presented. The UWB PA proposed in this paper uses a current-reused technique to enhance the gain at the upper end of the desired band, and the resistive feedback at the second stage is used to obtain gain flatness. The shunt-shunt feedback is used to enhance bandwi...

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking c...