Substrate noise generated by digital circuits on mixed-signal ICs can disturb the sensitiveanalog/RF circuits, such as Low Noise Amplifier (LNA), sharing the same substrate. This paperinvestigates the adverse impact of the substrate noise on a high frequency cascode LNA laid out on alightly doped substrate. By studying the major noise coupling mechanisms, a new and efficientmodeling method is p...

This paper presents an innovative CMOS structure for Differential Difference Transconductance Amplifiers (DDTA). While the circuit operates under extremely low voltage supply 0.5 V, circuit’s performance is improved thanks to using multiple-input MOS transistor (MI-MOST), bulk-driven, self-cascode and partial positive feedback (PPF) techniques. As a result, DDTA less complex, with high gain of ...

In this work, design of CMOS operational amplifiers (opamps) is discussed using a new technique of transistor sizing, called as Potential Distribution Method (PDM). PDM is a technique proposed to simplify analog design and is primarily based on voltage and current distribution at different nodes of a circuit. Apart from being technology independent, PDM is also free from complex mathematical ex...

Mixed and analog systems design with high performance suffers from many difficulties due to supply voltage, power consumption and area overhead. A need for low-voltage low-power operational amplifiers exists and used for some applications. This paper deals an effective OTA design for good PSRR, low-voltage, low-power and wide output voltage swing operational amplifier. Trying to combine an alte...

This paper presents the design and analysis of a 5.5 V Class-D stage used in two fully integrated watt-level, +32.0 dBm and +29.7 dBm, outphasing RF Power Amplifiers (PA) in standard 130 nm and 65 nm CMOS technologies. The Class-D stage utilizes a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V technologies without excessive device vol...

A class-AB rail-to-rail CMOS buffer amplifier is proposed and fabricated. The main circuit structure includes a bias circuit, a complementary folded-cascode differential input stage, a common-mode rejection ratio (CMRR) enhancement stage, and a class-AB output stage. With the complementary folded-cascode input stage, high input common-mode range (ICMR) and rail-to-rail output are realized. By u...