A highly integrated homodyne receiver has been demonstrated within a footprint of 1 cm. The receiver successfully receives 40 Gbit/s BPSK and error free is achieved up to 35 Gbit/s. Theoretical analysis has been also carried out showing the feasibility of integrated 16 QAM homodyne coherent receivers. OCIS codes: (250.5300) Photonic integrated circuits; (060.2840) Heterodyne; Optical phase-lock...

A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER< 10−12. It has better than 136fJ/b of power efficiency at 10Gb/s. The tota...

We provide an overview of the Riemann ζ-function with an eye to a proof of the functional equation that is non-standard and more accessible than those proofs readily available in modern texts. This is s survey note with the goal of a more elegant and transparent presentation of the salient features surrounding the functional equation for the ζ-function and the intimate connections with the Riem...

A low-power high-speed optical receiver in 28nm CMOS is presented. The design features a novel architecture combining a low-bandwidth TIA front-end, double-sampling technique and dynamic offset modulation. The low-bandwidth TIA increases receiver’s sensitivity while adding minimal power overhead. Functionality of the receiver was validated and the design is compared with a conventional 3-stage ...