Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable c...

Comparing and evaluating the performance of reconfigurable processors is a difficult task. For this research field to progress in a more meaningful and scientific fashion, there needs to be a method of measuring progress between different reconfigurable architectures as well as with respect to traditional computing technologies. This paper presents the Reconfigurable Architecture TEsting Suite,...

This paper presents an infrastructure to verify the functionality of the specific architectures generated by a high-level compiler, targeting dynamically reconfigurable hardware. Java, XML, and XSL technologies are used to support the infrastructure. As simulation engine we use Hades, an event driven Java based simulator. It results in a suitable scheme to test the designs generated by the comp...

Low power consumption or high execution speed is achieved by making an application specific design. However, today’s systems also require flexibility in order to allow running similar or updated applications (e.g. due to changing standards). Finding a good trade-off between reconfigurability and performance is a challenge. This work presents a design methodology to generate application-domain s...

Reconfigurable computing devices offer substantial improvements in functional density and yield versus traditional microprocessors, yet remain out of general-purpose use due in part to their difficulty of programming and lack of cross-device compatibility. This project presents a reconfigurable architecture which supports automated compilation and cross-device compatibility by virtualizing hard...

In this paper, the potential of reconfigurable hardware in wireless communication systems is evaluated. As most of the published works aim at the usage of reconfigurable architectures as a universal platform for different standards, the optimization capabilities of reconfiguration techniques for hardware modules within one standard are often not considered. This work focuses on the hardware opt...

The paper analyses different techniques that might be employed in order to solve various problems of combinatorial optimization and argues that the best results can be achieved by the use of software running on a general-purpose computer together with an FPGA-based reconfigurable co-processor. It suggests an architecture for a combinatorial coprocessor that is based on hardware templates and co...

Reconfigurable Computing (RC) uses reconfigurable logic devices such as FPGAs to assist generalpurpose computation. In order to make efficient use of FPGA resources, it is essential to size datapaths and functional units to the minimal possible bitwidth that will ensure correctness. Since the high-level languages used to program RC systems do not require (or even allow) the user to manually spe...