نتایج جستجو برای: pulse circuit

تعداد نتایج: 201257  

2014
G. Surendra Babu

The resonant power conversion having many advantages over conventionally adopted pulse width modulation that includes a high efficiency, low electromagnetic interference, small volume, low switching losses, and light weight of components due to a high switching frequency, and low reverse recovery losses in diodes owing to a low di/dt at switching instant. This paper presents the doubly loaded r...

2009
Ying-Yu Tzou

This paper presents a new circuit realization of the space-vector pulse-width modulation (SVPWM) strategy. An SVPWM control integrated circuit (IC) has been developed using the state-of-the-art field-programmable gate array (FPGA) technology. The proposed SVPWM control scheme can be realized using only a single FPGA (XC4010) from Xilinx, Inc. The output fundamental frequency can be adjusted fro...

2015
E. E. Bowles

This paper describes a scheme to control the intrapulse energy variations of long pulse bursts of an induction linac. Analog control over the electron beam injector current is exercised in such a way that accelerator beam load variations compensate for thermal impedance variations of the accelerator cell ferrites. Circuit topology and test data are presented. The circuit uses 64 planar triodes ...

2012
H. Canacsinh J. Fernando A. da Silva Sónia Ferreira Pinto Luis M. Redondo

This paper addresses the voltage droop compensation associated with long pulses generated by solid-stated based high-voltage Marx topologies. In particular a novel design scheme for voltage droop compensation in solid-state based bipolar Marx generators, using low-cost circuitry design and control, is described. The compensation consists of adding one auxiliary PWM stage to the existing Marx st...

Journal: :The Review of scientific instruments 2011
P D Nonn A P Blair K J McCollam J S Sarff D R Stone

A 10-MVA-scale resonant oscillator, powered by a pulse-forming network and switched with a pair of commutating mercury ignitrons, was developed for the MST reversed-field pinch plasma-confinement experiment. A novel feature of this circuit is its commutation mechanism, wherein each turning on of one ignitron causes a reverse voltage transient that turns off the other. Two of these oscillators a...

Journal: :IEEE Trans. VLSI Syst. 2003
Joong-Seok Moon William C. Athas Sigfrid D. Soli Jeffrey T. Draper Peter A. Beerel

We describe a new design technique for efficient harmonic resonant rail drivers. The proposed circuit implementation is coupled to a standard pulse source and uses only discrete passive components and no external dc power supply. It can thus be externally tuned to minimize the consumed power in the target IC. A new design technique based on current-fed voltage pulse-forming network theory is pr...

In the present work, four polymeric nanocomposite PNC coatings were prepared with different concentrations of yttrium aluminum garnet nanoparticles YAG-NPs in polyvinyl butyral PVB matrix. The corrosion protection of the PNC coatings applied on the carbon steel surface was investigated in 1.0 M HCl solution by electrochemical impedance spectroscopy EIS. The YAG-NPs were synthesized by pulse ele...

In this paper, a new open-switch fault diagnosis method is proposed for the six-phase AC-DC converter based on the difference between the phase current and the corresponding reference using an adaptive threshold. The open-switch faults are detected without any additional equipment and complicated calculations, since the proposed fault detection method is integrated with the controller required ...

2006
Tetsuya Asai Tetsuya Hirose Yoshihito Amemiya

An inhibitory network model that performs noise-shaping pulse-density modulation [1] was implemented with subthreshold analog MOS circuits, aiming at the development of ultralow-power Σ∆-type AD converters. Through circuit simulations, we evaluate the effects of the noise shaping produced by the network circuit. Keywords—VLSI, pulse density modulation, noise shaping, chaotic neural networks 1 M...

2001
Marco A. Peña Jordi Cortadella Enric Pastor Alexander Smirnov

The verification of a n-stage pulse-driven IPCMOS pipeline, for any n > 0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor. The correctness of the circuit highly depends on the timed behavior of its components and the environment. To verify the system, three techniques have been combined: (1) relative-timing-based verifi...

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