In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low p...

High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e...

In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm technology. The performance parameters such as delay, area, to...

A low-power, self-timed, CMOS array multiplier, optimized for asynchronous DSP but also applicable to synchronous DSP applications is presented. In order to reduce average power consumption, a strategy termed conditional-evaluation is introduced whereby addition is carried out only in rows of the carry-save array whose bit-product is non-zero. Simulation results are presented for a transistor-l...

Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers very...

In this paper, a new charge-recycling differential logic named split-level precharge differential logic (SPDL) is presented. It employs a new push–pull type output driver which is simple and separated from the NMOS logic tree. Therefore, it can improve energy efficiency, driving capability, and reliability compared with the previous differential logic structures which use cross-coupled inverter...

In this paper, a new low-voltage low-power CMOS 1-bit full adder circuit is proposed. The proposed full adder can provide a full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission full adder, and the recent low-voltage full adder. Based on the simulation results performed by HSPICE, the new low-voltage...

Multi-context architectures like NATURE enable low-power applications to leverage fast context switching for improved energy efficiency and lower area footprint. The NATURE architecture incorporates 16-bit reconfigurable DSP blocks for accelerating arithmetic computations, however, their fixed precision prevents efficient re-use in mixed-width arithmetic circuits. This paper presents an improve...

Dynamic pass-transistor logic (PTL), which combines pass-transistor logic with dynamic logic, is proposed for high-performance VLSI circuit design. The dynamic PTL holds the merits of fast evaluation characteristics as dynamic logic. Moreover, because a pre-charged scheme solves the weak logic ‘high’ problem of a static PTL, an additional level restoration circuit is not needed. An 8-bit multip...