This paper proposed an efficient phase-locked loop (PLL) that features zero steady-state error of phase and frequency under voltage sag, phase jump, harmonics, DC offsets and step-and ramp-changed frequency. The PLL includes the sliding Goertzel discrete Fourier transform (SGDFT) filter-based fundamental positive sequence component separator (FPSCS), the synchronousreference-frame PLL (SRF-PLL)...

Grid converters synchronized by phase-locked loops (PLLs) could suffer from stability problems, especially being connected to a weak grid or high penetration of converters. The existing literature assesses the paralleled PLL-synchronized at same point common coupling (PCC) using identical control and system parameters. However, in an actual grid, parameters are normally different due manufactur...

This work aims at analyzing three different techniques for synchronizing RF oscillators. These techniques are Injection Locking (ILO), Phase Locked Loop (PLL) and Injection Locked Phase Locked Loop (ILPLL). ILPLL, which is a combination of PLL and ILO, has superior noise performance –compared to all the restat medium frequency offsets and the same noise performance at low and high offsets. Furt...

An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional desi...

This document is meant to help individuals use the Cerebral Signal Phase Analysis toolbox which implements different methods for estimating the instantaneous phase and frequency of a signal and calculating some related popular quantities. The toolbox – which is distributed under the terms of the GNU GENERAL PUBLIC LICENSE as a set of MATLAB R © routines – can be downloaded at the address http:/...