Speculative execution and instruction reuse are two important strategies that have been investigated for improving processor performance. Value prediction at the instruction level has been introduced to allow even more aggressive speculation and reuse than previous techniques. This study suggests that using compiler support to extend value reuse to a coarser granularity than a single instructio...

Instruction set identification problem has been one of the major research topics in the last decade. Most of the solution proposals in the literature assume a fixed size register file with pre-specified input and output ports. On the other hand, reconfigurable hardware such as an FPGA has a variety of on-chip resources, which can be configured according to the requirements of the application. H...

The Instruction-Set extension problem has been one of the major topics in the last years and it is the addition of a set of new complex instructions to a given Instruction-Set. This problem in its general formulation requires an exhaustive search of the design space to identify the candidate instructions. This search turns into an exponential complexity of the solution. In this paper we propose...

This study investigated the effectiveness of colligational corpus-based instruction on enhancing the pragmalinguistic knowledge of speech act of request among Iranian intermediate EFL learners. The objective of the study was to find out whether or not providing students with corpora through using colligational instruction had any significant effects on enhancing their pragmalinguistic knowledge...

Like the design of any instruction, designing the Web as an instructional tool must include certain Moreover, online learning must provide a framework for producing a Incorporating interactivity and multimedia into web-based instruction. Web-based instruction provides teachers with a means of meeting the social needs of A framework for designing interactivity into Web-based instruction. *Techno...

In this paper a dynamic task scheduling unit for many-core systems The CoreManager instruction set extensions are developed with the tool flow. An instruction set architecture extension for supporting fine-grain thread scheduling and execution is proposed. Task level parallelization is supported by various programming models core and the Distributed Thread Scheduling Unit (DTSU), one per node. ...

-It has been known that loops constitute the most executed segments of programs and therefore are the best candidates for hardware implementation. We present a set of profiling tools that are specifically dedicated to loop profiling and do support combined function and loop profiling. One tool relies on an instruction set simulator and can therefore be augmented with architecture and micro-arch...

Given an instruction set, the superoptimizer finds the shortest program to compute a function. Startling programs have been generated, many of them engaging in convoluted bit-fiddling bearing little resemblance to the source programs which defined the functions. The key idea in the superoptimizer is a probabilistic test that makes exhaustive searches practical for programs of useful size. The s...

With this scheme, a simple processor might take 4 cycles per instruction (CPI = 4). processors, such as IBM's 801 research prototype, the MIPS R2000 (based on to pipeline a RISC because its reduced instruction set means the instructions This simple (and fun) classification of design styles first appeared in a 1993. The two processor classifications are the Reduced Instruction Set Computer The p...