Network-on-Chip (NoC) has been introduced to meet the communication challenges for on chip multi-processors and the bandwidth of NoC takes a significant role in area and power consumption of overall system. In order to minimize the bandwidth requirement of NoC, a mapping method is proposed to schedule the tasks of an application onto NoC architecture. More precisely, given the application task ...

A generic analytical performance model of singlechannel wormhole routers is presented using the M/D/1/B queuing theory. Compared with previous work, the flowcontrol feedback mechanism is studied in detail, and a computing method bases on Markov chain for the flowcontrol feedback probability is proposed. Compared with BookSim, a well-known cycle-accurate Network-on-Chip (NoC) simulator, this mod...

Approaching ideal wire latency using a network-on-chip (NoC) is an important practical problem for many-core systems, particularly hundreds-cores. Although other researchers have focused on optimizing large meshes, bypassing or speculating router pipelines, or creating more intricate logarithmic topologies, this paper proposes a balanced combination that trades queue buffers for simplicity. Pre...

The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless No...

As chip complexity keeps increasing in system-on-chip (SoC), the on-chip interconnect has become a critical issue for large-scale chip design. It has been proposed that the packet-switched network exchanging messages between intellectual property (IP) cores is a viable solution for the SoC interconnect problem. The design of the router in such network-on-chip (NoC) architectures is the key to h...

Electrical discharge machining process is one of the most Applicable methods in Non-traditional machining for Machining chip in Conduct electricity Piece that reaching to the Pieces that have good quality and high rate of machining chip is very important. Due to the rapid and widespread use of alloy DIN1.2080 in different industry such as Molding, lathe tools, reamer, broaching, cutting guillot...

The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational perf...

Large-scale photonic integration circuits (PICs) have been demonstrated on InP [1] and Si [2–5] substrates for data communications. Silicon PICs 3D integrated with electronic integrated circuits promise future high-speed and cost-effective optical interconnects to enable Exascale performance computers and datacenters [5]. For realistic intra-chip and inter-chip optical links, the bandwidth dens...

Article history: Received 11 June 2012 Received in revised form 22 April 2013 Accepted 30 June 2013 Available online 6 July 2013